JEDEC Relaxes HBM4 Package Height to 775 µm, Enabling 12-Hi/16-Hi Stacks Without Immediate Cu-Cu Hybrid Bonding

August 17, 2026

Exponential Industry USA

Overview

JEDEC has relaxed the HBM4 package height specification from 720 µm to 775 µm, allowing for 12-Hi and 16-Hi stack HBM modules without immediate reliance on Cu-Cu hybrid bonding. HBM utilizes 3D stacked DRAM dies connected via TSVs and microbumps, interfacing with accelerators through 2.5D interposers like TSMC CoWoS. Vendor-specific bonding methods include SK Hynix’s MR-MUF and Samsung/Micron’s TCB-NCF.

In Depth

Key Findings

JEDEC (Joint Electron Device Engineering Council) has made a significant decision to relax the HBM4 (High Bandwidth Memory 4) package height specification, increasing it from the previous 720 µm to 775 µm. This modification is a crucial step toward enabling 12-Hi and 16-Hi stack HBM modules without the immediate necessity of adopting the more complex copper-to-copper (Cu-Cu) hybrid bonding technology. This provides manufacturers with greater flexibility to increase HBM capacity and performance.

Technical / Clinical Details

HBM is an advanced memory technology that involves vertically stacking multiple DRAM dies through TSVs (Through-Silicon Vias) and microbumps. These stacked HBM dies are then connected to logic chips, such as GPUs and AI accelerators, via a 2.5D interposer, exemplified by TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) technology. This architecture delivers extremely high memory bandwidth and low power consumption. JEDEC’s package height relaxation facilitates HBM manufacturers in stacking more dies while temporarily mitigating the increase in packaging complexity and cost, thereby achieving higher capacities. Current HBM production employs vendor-specific bonding methods; for instance, SK Hynix uses MR-MUF (Mass Reflow-Molded Underfill), while Samsung and Micron utilize TCB-NCF (Thermo-Compression Bonding with Non-Conductive Film). These techniques are optimized to ensure high connection reliability at fine bump pitches.

Background & Context

The rapid advancements in high-performance computing fields such as AI, HPC, and data centers have exponentially increased the demand for memory bandwidth and capacity. HBM, with its superior performance, has become the de facto standard for meeting these requirements. JEDEC’s specification relaxation aims to foster further HBM evolution, establishing an environment for future AI accelerators to process larger models more efficiently. Furthermore, with the accelerated adoption of chiplet architectures, heterogeneous integration of multiple dies within a single package is becoming commonplace, driving demand for interconnect precision below 5 microns. This trend further underscores the critical importance of HBM and advanced packaging technologies.

Strategic Significance & Outlook

The relaxation of HBM4 package height temporarily reduces a technical barrier for HBM manufacturers in developing and mass-producing higher-capacity HBM products. This could accelerate the market introduction cycle for HBM and further drive innovation in the AI and HPC sectors. While a transition to more advanced connection technologies like Cu-Cu hybrid bonding is inevitable in the long term, this relaxation serves as a technological bridge during the interim period. The evolution of HBM is expected to continue stimulating innovation in back-end packaging technologies, material development, and equipment advancement, playing an indispensable role in enhancing the performance of next-generation AI infrastructure.

Source: https://exponentialindustry.com/blog/2026-08-11-hbm-stacking-architecture-packaging-market-guide/

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