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TSMC Narrows CoWoS Supply-Demand Gap from 20% to 10% by End of 2026; NVIDIA to Adopt Next-Gen CoPoS for 2028-2029 Mass Production

Moomoo Singapore
Overview
TSMC is accelerating advanced packaging capacity expansion, projecting its CoWoS supply-demand gap to significantly narrow from approximately 20% to 10% by the end of 2026. Concurrently, research and development for its next-generation CoPoS (Chip-on-Panel-on-Substrate) packaging platform are progressing, with NVIDIA’s Feynman platform reportedly becoming the first customer for CoPoS, targeting mass production by 2028-2029. TrendForce forecasts TSMC’s monthly CoWoS production capacity to reach 120,000-140,000 wafers by 2026.
In Depth

Key Findings

TSMC is aggressively expanding its CoWoS (Chip on Wafer on Substrate) advanced packaging capacity, aiming to significantly reduce the current supply-demand gap of approximately 20% to around 10% by the end of 2026. Simultaneously, the company is making substantial progress in the research and development of its next-generation packaging platform, CoPoS (Chip-on-Panel-on-Substrate). Reports indicate that NVIDIA’s Feynman platform is slated to be the first customer to adopt CoPoS, with mass production targeted for 2028-2029, promising to further advance AI chip performance and stabilize supply.

Technical & Economic Details

The projected narrowing of the CoWoS supply-demand gap is attributed to TSMC’s massive investments across multiple sites and optimization of its production processes. According to TrendForce, TSMC’s monthly CoWoS production capacity is expected to reach 120,000-140,000 wafers by 2026, which will partially catch up with the escalating AI chip demand. CoPoS technology aims for even higher integration density and improved cost efficiency compared to CoWoS by integrating chips on larger substrates (panels). NVIDIA’s adoption of CoPoS for its Feynman platform underscores the critical importance of this new technology for high-end AI accelerators. The commercialization of CoPoS is expected to alleviate current CoWoS constraints, enabling the construction of even larger-scale AI systems.

Background & Context

The rapid evolution of AI has dramatically increased the demand for high-performance computing (HPC) chips and High Bandwidth Memory (HBM). The advanced packaging technologies required to integrate these components have become a significant bottleneck in the semiconductor supply chain. TSMC has continuously invested in and innovated its technology to address this bottleneck. The improved CoWoS supply is expected to partially ease the AI chip shortage, accelerating the deployment of AI infrastructure. However, as AI chip performance requirements continue to escalate, the need for even more advanced packaging technologies like CoPoS grows, indicating that the industry may face new bottlenecks down the line.

Strategic Significance & Outlook

The reduction in TSMC’s CoWoS supply gap and the introduction of CoPoS will have a profound impact on the AI chip market. In the short term, improved supply stability will accelerate AI hardware deployment and boost the growth of key players like NVIDIA. In the medium to long term, NVIDIA’s early adoption of CoPoS could establish this new technology as an industry standard. The mass production of CoPoS has the potential to further enhance AI chip integration and performance, revolutionizing the design of next-generation AI applications and data centers. However, new challenges, such as establishing the CoPoS supply chain and stabilizing yields, are anticipated, making future developments in this area highly anticipated.

Source: https://www.moomoo.com/news/post/71534056/ai-computing-capacity-bottleneck-easing-report-taiwan-semiconductor-s-cowos

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