TSMC Unveils SoIC 3D Stacking Roadmap: Achieving 4.5µm Pitch by 2029, Enabling Face-to-Face Chiplet Integration for Fujitsu Monaka CPU

専門メディア Taiwan

Overview

TSMC has revealed its SoIC (System on Integrated Chips) 3D stacking roadmap, targeting a 4.5-micron pitch by 2029, down from today’s 6 microns. This advanced face-to-face (F2F) chiplet stacking technology, part of the second-generation SoIC, is poised to benefit high-performance CPUs like Fujitsu’s Monaka, significantly boosting vertical interconnect density for next-generation AI/HPC chips.

In Depth

Background

The relentless pursuit of higher performance in AI and High-Performance Computing (HPC) has driven the semiconductor industry beyond traditional 2D scaling, making 3D integration technologies increasingly vital. TSMC’s System on Integrated Chips (SoIC) is a foundational 3D stacking solution that enables ultra-fine pitch inter-die bonding, offering superior bandwidth and lower latency compared to conventional packaging methods that rely on wire bonding or microbumps. This vertical integration is crucial for assembling complex chiplet-based architectures that demand maximum density and minimal communication overhead between constituent dies.

Key Findings / Results

TSMC has published an ambitious roadmap for its SoIC 3D stacking technology, detailing plans to shrink the inter-die connection pitch from the current 6 micrometers (µm) to an impressive 4.5 µm by 2029. This pitch reduction directly translates to a significant increase in vertical interconnect density, enhancing data throughput and overall system performance. A cornerstone of this advancement is the second-generation SoIC technology, which introduces face-to-face (F2F) stacking. F2F bonding allows direct electrical connection between the active surfaces of two dies, minimizing wiring layers and optimizing electrical characteristics. Fujitsu’s upcoming Monaka supercomputer CPU is expected to be an early adopter of this F2F chiplet stacking, leveraging its benefits for enhanced performance. For instance, the A14-to-A14 SoIC, slated for mass production in 2029, is projected to deliver 1.8 times the inter-die I/O density compared to N2-on-N2 SoIC.

Technical Significance & Outlook

The continued pitch miniaturization of SoIC represents a critical technical leap for AI/HPC architectures. Higher density vertical interconnects facilitate the creation of more sophisticated Systems-on-Chips (SoCs) that integrate various logic chiplets or logic with memory in a tightly coupled manner. This enables improvements in computational power, reductions in power consumption, and smaller form factors, driving innovation across data centers, edge AI, and supercomputing applications. TSMC’s SoIC technology is already implemented in products like AMD’s Instinct MI300 series, indicating its proven viability for high-end applications. This roadmap reinforces the trend towards heterogeneous integration and the chiplet ecosystem, allowing designers to fabricate specialized functional blocks on optimal process nodes and integrate them seamlessly through advanced packaging. The success of SoIC will be a key enabler for the next generation of AI hardware, pushing the boundaries of what is possible in computing.