TSMC Accelerates CoWoS and SoIC Expansion to Quell AI Chip Bottleneck, Targets 4x Capacity by 2026

FinancialContent – Stock Market Taiwan

Overview

TSMC is aggressively expanding its CoWoS and SoIC advanced packaging capacity to address the soaring demand for AI chips, aiming to increase monthly wafer output from approximately 35,000 units in late 2024 to 130,000 by the end of 2026. This nearly fourfold increase is a direct response to urgent orders from major customers like Nvidia and Google, critical for overcoming severe bottlenecks in the AI supply chain. The strategic move involves new facility constructions and re-purposing existing lines, solidifying TSMC’s role as a key enabler of next-generation AI accelerators.

In Depth

Background: AI Boom Exacerbates Advanced Packaging Bottlenecks

The explosive growth of generative AI technologies has propelled demand for AI chips in data centers and high-performance computing (HPC) to unprecedented levels. This surge has, in turn, created a severe bottleneck in the supply of advanced packaging technologies, particularly TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System-on-Integrated-Chips). These techniques are indispensable for integrating multiple chiplets at high densities and collaborating with High Bandwidth Memory (HBM) to maximize the performance of AI accelerators. The intense market demand coupled with existing supply constraints has compelled TSMC to undertake urgent capacity expansion measures.

TSMC’s Aggressive CoWoS/SoIC Capacity Expansion Plan

To alleviate the CoWoS and SoIC supply shortage, TSMC is executing a highly ambitious capacity expansion strategy. The company aims to boost its monthly CoWoS production capacity from approximately 35,000 wafers in late 2024 to an impressive 130,000 wafers by the end of 2026—nearly a fourfold increase. This aggressive expansion encompasses several strategic initiatives:

• New Fab and Plant Constructions: TSMC is building 18 new fabs and advanced packaging facilities globally. Specific plans include dedicating a new P2 plant at its AP8 factory in Southern Taiwan Science Park for CoWoS production and converting a portion of the SoIC line at the AP7 factory in Chiayi to CoWoS production.
• Repurposing 8-inch Wafer Fabs: Plans are underway to convert some existing 8-inch wafer fabs into advanced packaging facilities, maximizing existing resources to achieve rapid capacity augmentation.
• Technology Roadmap Disclosure: At its 2026 Technology Symposium, TSMC detailed advancements in leading-edge process nodes, 3DFabric advanced packaging technologies, global expansion strategies, and the latest progress in AI-powered smart manufacturing, underscoring its commitment to future innovation and capacity growth.

Industry Impact and Strategic Significance

TSMC’s substantial expansion of CoWoS/SoIC capacity is set to have a profound impact on the entire AI supply chain. Nvidia has reportedly secured over 60% of TSMC’s CoWoS capacity for 2025-2026, reinforcing Nvidia’s dominance in the AI chip market while also providing a crucial supply source for other AI chip developers. Furthermore, the ripple effect of this capacity crunch has benefited Taiwanese OSAT (Outsourced Semiconductor Assembly and Test) firms such as ASE and King Yuan Electronics, who are also investing heavily in advanced testing capabilities for AI chips and developing CoWoS-related technologies (e.g., ASE’s CoWoP). TSMC’s strategy not only addresses a critical bottleneck but also lays the foundation for next-generation AI hardware, driving the growth of the entire semiconductor industry with significant strategic implications.