ASML, TSMC, and Imec Announce Breakthrough 300mm Integration for 2D Material Transistors, Advancing Next-Gen Logic

June 28, 2026

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Overview

Semiconductor industry leaders ASML, TSMC, and imec have unveiled a 300mm wafer integration process for 2D material transistors (MoS2 nFET and WSe2 pFET) featuring a 50nm contact poly pitch (CPP). This groundbreaking achievement moves 2D material devices from lab-scale to industrial viability, paving the way for high-density logic, backend, and wafer-backside applications and promising significant performance and efficiency gains for future semiconductor technologies.

In Depth

Background

The relentless pace of miniaturization in the semiconductor industry, historically driven by Moore’s Law, is now confronting fundamental physical and economic limits. This necessitates an urgent pivot towards novel materials and innovative architectures beyond conventional silicon. Two-dimensional (2D) materials have long been investigated as promising candidates to succeed silicon in future transistor technologies, yet their industrial adoption has been hampered by significant manufacturing challenges. Chief among these are the uniform formation of atomic-scale thin films over large areas and seamless integration into established semiconductor manufacturing processes. A powerful collaboration between key industry players—ASML, bringing its advanced lithography expertise; TSMC, contributing its unparalleled manufacturing capabilities; and imec, leveraging its cutting-edge R&D prowess—has been instrumental in overcoming these critical barriers. This foundational development is poised to directly influence the design and production of next-generation AI chips, mobile devices, and IoT hardware, fundamentally reshaping the trajectory of the semiconductor industry.

Key Findings

ASML, TSMC, and imec have jointly announced a pivotal development: a 300mm wafer integration process for 2D material-based transistors, specifically molybdenum disulfide (MoS2) nFETs and tungsten diselenide (WSe2) pFETs, achieved with an impressive 50nm Contact Poly Pitch (CPP). This breakthrough is a crucial leap, moving 2D material transistor technology from laboratory experimentation to industrial-scale manufacturing, unlocking its potential for highly miniaturized logic, backend-of-line (BEOL), and wafer-backside applications.

Conventional silicon transistors are rapidly approaching fundamental physical limits, making further performance gains and miniaturization increasingly challenging. Two-dimensional (2D) materials, particularly transition metal dichalcogenides (TMDs), offer a compelling alternative due to their atomic-scale thinness, high carrier mobility, and superior electrostatic control, positioning them as prime candidates for next-generation transistor channels. The successful establishment of this 300mm wafer integration process directly addresses several critical technical hurdles:

50nm Contact Poly Pitch (CPP): This metric defines the spacing between transistor gates and contacts, with 50nm signifying extremely fine-grained fabrication. Such tight integration is essential for achieving high transistor density and maximizing chip area efficiency, critical for advanced nodes.
300mm Wafer Integration: The ability to consistently fabricate 2D material transistors on industry-standard 300mm (12-inch) wafers is a monumental step towards commercialization. This achievement promises to significantly reduce manufacturing costs and dramatically scale up production capacity, essential for high-volume applications.
MoS2 nFET and WSe2 pFET Integration: Molybdenum disulfide (MoS2) exhibits n-type semiconductor characteristics, while tungsten diselenide (WSe2) displays p-type properties. The successful integration of both materials at an industrial scale, enabling the formation of complementary metal-oxide-semiconductor (CMOS) circuits, is vital for realizing lower power consumption and higher performance logic devices. This represents a significant move beyond prior lab-scale demonstrations.
Backend and Wafer-Backside Applications: The intrinsic atomic thinness of 2D materials makes them uniquely suitable for integration beyond the conventional front-side of the wafer. Their deployment in backend (interconnect layers) and on the wafer backside opens new avenues for design freedom in advanced 3D stacked chips and chiplet architectures. This capability is expected to accelerate the development of high-density, high-performance computing (HPC) and artificial intelligence (AI) chips.

This milestone represents a profound step towards the practical implementation of 2D material semiconductors. Looking forward, this technology is poised for further refinement, with anticipated applications in even finer process nodes (e.g., sub-3 nm) and performance optimization through novel combinations of 2D materials. This breakthrough will galvanize the convergence of materials science and process technology within the semiconductor industry, delivering the high-performance, high-efficiency hardware platforms indispensable for the continued evolution of AI and other demanding applications. Ultimately, this foundational innovation is set to dramatically enhance the performance of electronic devices across the spectrum, from personal smartphones to hyperscale data centers, thereby enriching our digital lives.

Source: https://www.reinraum.de/en/news/asml-tsmc-and-imec-make-industrial-grade-transistors-from-2d-materials-more-tangible-through-groundbreaking-300-mm-integration.html

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