TSMC and Kinsus Jointly Developing New AI Chip Packaging Technology Akin to Intel’s EMIB to Address CoWoS Capacity Constraints

August 2, 2026

Tech in Asia Singapore

Overview

TSMC is reportedly collaborating with Kinsus to develop a novel AI chip packaging technology, resembling Intel’s Embedded Multi-die Interconnect Bridge (EMIB), to alleviate the tight supply of CoWoS capacity for high-end AI processors from customers like Nvidia and AMD. This new approach substitutes a full silicon interposer with smaller silicon bridges directly on the package substrate, aiming to reduce costs, improve yield, and enhance scalability for large multi-die AI packages. The initiative is a critical step towards resolving a key bottleneck in AI chip manufacturing.

In Depth

Key Findings

TSMC is reportedly collaborating with Kinsus to develop a new AI chip packaging technology similar to Intel’s Embedded Multi-die Interconnect Bridge (EMIB). This strategic move addresses the pressing issue of limited CoWoS (Chip-on-Wafer-on-Substrate) capacity, which is crucial for packaging high-end AI processors for key clients such as Nvidia and AMD.

Technical and Clinical Details

Traditional CoWoS technology, while highly effective for integrating multiple dies, relies on a full silicon interposer, which contributes to higher manufacturing costs, yield challenges, and capacity constraints. The EMIB-like approach bypasses the need for a full interposer by embedding smaller silicon bridges directly into the package substrate. This method allows for high-density interconnections between chips while offering several advantages: reduced manufacturing costs due to simplified processes, improved yields, and enhanced scalability for larger multi-die AI packages. The ability to efficiently integrate more chiplets is expected to significantly boost the performance and integration density of future AI accelerators, making them more powerful and cost-effective.

Background and Industry Context

The explosive growth of artificial intelligence has led to an unprecedented demand for high-performance AI chips. Nvidia’s GPUs and AMD’s AI accelerators, in particular, have become indispensable components in data centers and cloud AI services. However, the advanced packaging required for these chips, especially CoWoS, has faced significant production capacity limitations. This supply bottleneck has emerged as a critical constraint slowing the overall deployment of AI infrastructure. Consequently, leading foundries like TSMC have been under pressure to innovate and develop alternative packaging solutions to meet the burgeoning market demand.

Strategic Significance and Outlook

The joint development of this new packaging technology by TSMC and Kinsus is paramount for alleviating AI chip manufacturing bottlenecks and accelerating the mass production of next-generation AI hardware. A successful implementation of EMIB-like technology would lead to the availability of more powerful and cost-efficient AI processors, further driving the adoption and evolution of AI across industries. This development stands to benefit not only AI chip design companies such as Nvidia and AMD but also data center operators and AI application developers who rely on advanced hardware. The industry will be closely watching the maturation of this technology and the establishment of its mass production capabilities, as it could reshape the competitive landscape of AI hardware manufacturing.

Source: https://www.techinasia.com/news/tsmc-explores-new-ai-chip-packaging-with-kinsus

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