AI Accelerates Shift to Panel Level Packaging (PLP) and Glass Core Substrates, Positioning Them as Pillars of Next-Gen Packaging

August 17, 2026

IEEE / Presentation USA

Overview

Driven by soaring demand from AI, automotive electronics, and consumer devices, advanced packaging is a critical enabler for enhanced performance, higher integration, and miniaturization in semiconductors. Panel Level Packaging (PLP) and glass core substrates are emerging as key next-generation platforms shaping the industry’s future. While PLP promises reduced manufacturing costs and large package scalability, challenges like warpage control and thermal robustness persist. These technologies are poised to deliver indispensable solutions for high-performance chips in the AI era.

In Depth

Key Findings

With the surging demand from Artificial Intelligence (AI), automotive electronics, and consumer devices, advanced packaging is now recognized as the most critical driver for achieving enhanced chip performance, higher integration, and miniaturization in the semiconductor industry. Within this context, two innovative technologies, Panel Level Packaging (PLP) and glass core substrates, are emerging as pivotal platforms set to define the future direction of semiconductor packaging. PLP garners significant anticipation for its potential to reduce manufacturing costs and accommodate ultra-large packages, while glass core substrates are expected to offer high-density routing and superior electrical properties, playing an indispensable role in next-generation high-performance chips.

Technical / Clinical Details

Panel Level Packaging (PLP) involves manufacturing and packaging chips on larger square or rectangular panels instead of traditional circular wafers. This approach promises improved material utilization efficiency during manufacturing, potentially reducing final packaging costs by increasing the number of chips processed per unit area. PLP is particularly well-suited for large-scale heterogeneous integration, such as AI processors and HBM (High Bandwidth Memory), especially in fan-out packaging. However, PLP still faces technical challenges, including warpage control in large-area substrate manufacturing, high-precision lithography, and ensuring thermal robustness. On the other hand, glass core substrates, compared to conventional organic substrates, enable finer routing patterns, offer low dielectric loss, high mechanical strength, and excellent thermal stability. These characteristics improve high-frequency signal transmission quality, making them ideal platforms for AI chips and HPC applications requiring high-density interconnects. Glass also exhibits a lower coefficient of thermal expansion than organic materials, which is expected to reduce thermal stress between different materials and enhance package reliability.

Background & Context

As the slowdown of Moore’s Law becomes increasingly evident, the semiconductor industry is seeking new approaches to achieve performance improvements beyond transistor miniaturization. Advanced packaging is one of the primary solutions to this challenge, with the explosive growth of AI accelerating its development and adoption. AI chips require high-performance processors, large-capacity and high-bandwidth memory, and efficient packaging technologies to integrate them for rapid data processing. PLP and glass core substrates are positioned as next-generation solutions that break through the limitations of conventional packaging technologies to meet these demands. The shift towards these technologies significantly impacts semiconductor equipment manufacturers, material suppliers, and the entire design flow, prompting a transformation across the entire supply chain.

Strategic Significance & Outlook

Panel Level Packaging and glass core substrates will become indispensable technologies for manufacturing high-performance semiconductors in the AI era. PLP offers unique strengths in manufacturing cost and economies of scale, while glass core substrates excel in electrical performance and reliability. Over the next few years, further advancements in warpage control, thermal design, and cost-effective mass production techniques for these technologies are anticipated. The maturation of these technologies will enable significant leaps in semiconductor performance across AI accelerators, data centers, edge AI devices, and autonomous vehicles, sparking a new wave of innovation. The industry as a whole must continue collaborative efforts to overcome the challenges these technologies face and maximize their potential.

Source: https://events.vtools.ieee.org/m/541765

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