Glass Substrates Emerge as Next-Generation Solution to AI Chip Packaging Bottleneck

TrendForce Taiwan

Overview

Glass substrates are gaining significant traction as a next-generation material poised to overcome the limitations of traditional organic substrates and resolve critical bottlenecks in AI chip packaging. Offering superior thermal and mechanical properties, glass effectively minimizes warpage during the integration of large dies. Major industry players like Intel, TSMC, Samsung, and Rapidus are actively developing glass interposer and glass core substrate solutions, with SK Absolics targeting mass production by 2026, signaling accelerated commercialization.

In Depth

Background: Packaging Challenges for High-Performance AI Chips

The unprecedented demand for high-performance AI chips, driven by the rapid evolution of artificial intelligence, necessitates advanced packaging solutions that can accommodate increasingly larger die sizes, numerous cores, vast caches, and high-density High Bandwidth Memory (HBM) integration. Conventional organic substrates present several critical challenges for these large chips, including significant warpage issues, inherent limitations in signal transmission, difficulties in thermal management, and constraints in fine-pitch processing. These limitations collectively form a bottleneck in AI chip packaging, prompting the semiconductor industry to seek innovative next-generation packaging materials and structures.

Technical Advantages and Applications of Glass Substrates

Glass substrates are emerging as a highly promising solution to break through the AI chip packaging bottleneck, offering distinct technical advantages:

• Superior Thermal and Mechanical Stability: Glass exhibits higher thermal stability and rigidity compared to organic substrates, effectively suppressing warpage that typically occurs during the integration of large dies. This property is crucial for achieving high yields and reliability in complex heterogeneous integration and 3D stacking processes.
• High-Density Wiring and Electrical Performance: The exceptional flatness of glass substrates makes them ideal for forming ultra-fine wiring patterns. Furthermore, their low dielectric loss characteristics minimize signal degradation during high-speed data transmission, allowing AI chips to achieve their maximum performance potential.
• CTE Alignment with Silicon: With a coefficient of thermal expansion (CTE) relatively close to silicon (3–8 ppm/°C), glass significantly minimizes thermal stress-induced issues between different materials when integrating large components like GPUs and HBM. This presents a considerable advantage over traditional organic substrates and even silicon interposers.
• Potential for Cost Reduction: In the long term, utilizing larger glass panels compared to silicon wafers holds the promise of reducing manufacturing costs for advanced packages.

Leading semiconductor companies are actively embracing glass substrates. Intel announced its commitment to adopting glass substrates for advanced packaging in 2023 and showcased samples combining EMIB packaging with glass core substrates at NEPCON Japan in January 2026. TSMC, Samsung, and Japan’s Rapidus are also developing glass interposer solutions. Notably, SK Absolics in Korea aims for mass production of glass substrates by 2026, indicating an accelerated path to commercialization.

Industry Impact and Future Outlook

The adoption of glass substrates is expected to significantly enhance AI chip performance and cost-efficiency, potentially establishing a new standard for semiconductor packaging. This will enable AI accelerators to deliver more computational power with less energy, leading to reduced operational costs and improved sustainability for data centers. Moreover, it will drive further advancements in chiplet technology and heterogeneous integration, accelerating the development of high-performance semiconductors optimized for diverse applications. The mass production and widespread adoption of glass substrate technology represent a pivotal trend poised to support the evolution of the next-generation semiconductor industry, warranting continuous close observation.