Key Findings
Samsung Electronics unveiled groundbreaking research on the industry’s smallest “3D stacked FET” (Field-Effect Transistor) technology at the 2026 VLSI Symposium. This presentation was honored as the Best Paper among over 1,000 submissions, marking a significant achievement. This novel 3D stacked transistor architecture fundamentally redefines how transistors are arranged, promising dramatic improvements in performance and power efficiency for next-generation semiconductors designed for Artificial Intelligence (AI) and High-Performance Computing (HPC).
Technical / Clinical Details
- 3D Stacked Architecture: Samsung’s 3D stacked FET deviates from conventional planar transistor layouts by adopting a vertical stacking structure. This innovation enables a significant increase in transistor density within a limited silicon footprint, overcoming the traditional scaling limitations of 2D designs.
- Introduction of Nanosheet Channels: The research team implemented three “nanosheet channels” within each of the two vertically stacked transistors. Nanosheet channels expand the pathway for current flow and increase the contact area with the gate, thereby improving current driving capability and enhancing gate control. This design maximizes the “on-state” current and minimizes the “off-state” leakage current, achieving both high performance and low power consumption simultaneously.
- Enhanced Performance and Power Efficiency: This 3D stacked FET technology enables the creation of smaller, denser chips. It is particularly expected to deliver performance superior to existing technologies for applications demanding immense data processing power and high power efficiency, such as AI accelerators and HPC processors. While specific percentage improvements in performance were not quantified, the increased integration density and efficient current control are anticipated to lead to faster processing speeds and substantial reductions in power consumption.
Background & Context
The semiconductor industry is grappling with the physical limits of Moore’s Law, finding it increasingly challenging to achieve performance improvements solely through transistor miniaturization. Consequently, manufacturers are intensely focused on developing 3D stacking technologies and novel transistor structures. Samsung Electronics has been a leader in Gate-All-Around (GAA) FET technology, and this 3D stacked FET represents a further evolution of its technological innovation. With the explosive growth in demand for AI and data centers, chip performance and power efficiency have become paramount, and Samsung aims to establish a competitive advantage with this new technology.
Strategic Significance & Outlook
Samsung’s 3D stacked FET technology holds the potential to revolutionize semiconductor design and manufacturing for future advanced process nodes. If this technology moves into mass production, it is expected to dramatically enhance the performance and power efficiency of all next-generation devices, including AI chips, HPC, and mobile processors. Samsung will likely further strengthen its leadership in the global market by offering more powerful and energy-efficient semiconductor solutions, building on this achievement. This research marks a critical step forward in pioneering the next frontier of semiconductor technology.
Source: https://www.mk.co.kr/en/business/12076635
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