New Underfill Material Enables High-Performance Chiplet Integration in Fan-Out Wafer-Level Packaging

July 5, 2026

Semiconductor Packaging News Global

Overview

A new underfill material designed for Fan-Out Wafer-Level Packaging (FOWLP) has been developed, enabling next-generation high-performance chiplet integration. This material combines excellent fine-gap filling capabilities, low stress characteristics, and high reliability. It significantly enhances the integration density and electrical performance of chiplets for AI processors and High-Performance Computing (HPC), accelerating further advancements in the semiconductor industry.

In Depth

Key Findings

To enable next-generation high-performance chiplet integration, a novel underfill material specifically engineered for Fan-Out Wafer-Level Packaging (FOWLP) has been developed. This groundbreaking material combines three critical performance attributes at a high level: exceptional filling capability for minute gaps, low-stress characteristics that minimize stress generation after encapsulation, and high long-term reliability. This innovation significantly boosts the integration density and electrical performance of chiplets for AI processors and High-Performance Computing (HPC), establishing a new benchmark in semiconductor packaging technology.

Technical Details

Fine Gap Filling: Possesses low viscosity and high flowability, allowing for uniform, void-free filling even in extremely narrow inter-chip gaps and under-bump spaces. This maximizes bonding quality in high-density chiplet arrangements.
Low Stress Characteristics: Optimizes volumetric shrinkage during curing and the coefficient of thermal expansion (CTE) to minimize mechanical stress on chiplets. This prevents chip damage and package warpage, contributing to improved yield and reliability. Simulations reportedly show approximately a 20% reduction in stress compared to conventional underfills.
High Reliability: Exhibits excellent resistance to thermal cycling, high-humidity environments, and external impacts, ensuring the long lifespan and stable operation of chiplet-integrated devices. This is particularly crucial for mission-critical applications.
Process Compatibility: Can be easily integrated into standard FOWLP processes, with rapid cure times contributing to increased production throughput.

Background & Context

As the limits of Moore’s Law are approached, advanced packaging technologies such as chiplet integration and FOWLP are becoming key drivers for the evolution of high-performance applications like AI, HPC, and data centers. FOWLP offers high I/O density and superior thermal management, but achieving high-quality integration of multiple, minute chiplets demands advanced underfill materials. Traditional underfills have presented challenges such as incomplete filling of fine gaps and stress concentration on chips, acting as a bottleneck to performance enhancement.

Strategic Significance & Outlook

The advent of this new underfill material significantly expands the possibilities of chiplet integration via FOWLP, directly contributing to the performance enhancement of next-generation AI processors and server CPUs. This will lead to dramatic improvements in computing power, reduced power consumption, and device miniaturization, accelerating the development of various cutting-edge technologies such as autonomous driving, cloud computing, and edge AI. In the future, this technology is expected to become a standard material in semiconductor packaging as further multi-layering and heterogeneous integration advance, strengthening the overall competitiveness of the semiconductor ecosystem.

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