Intel’s EMIB-T Emerges as CoWoS Alternative, New XBM Memory Architecture to Alleviate AI Memory Bottleneck

July 12, 2026

Tom’s Hardware USA

Overview

Intel’s 2.5D packaging technology, EMIB-T, is emerging as a credible alternative to TSMC’s CoWoS for large-package AI accelerators, expanding validation for 36/35 µm bump pitch to 4.5x reticle silicon packages, targeting certification by late 2026. Furthermore, Intel has patented a new XBM memory architecture that ditches HBM’s costly silicon interposer, utilizing a backend-transistor DRAM stack with UCIe links and built-in repair, demonstrating a multi-faceted approach to easing the AI memory bottleneck.

In Depth

Key Findings

Intel’s advanced 2.5D packaging technology, EMIB-T (Embedded Multi-die Interconnect Bridge-Tile), is rapidly gaining traction as a reliable alternative to TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) for large-package AI accelerators. EMIB-T is expanding its validation for 36/35 µm bump pitch to 4.5x reticle-sized silicon packages, with certification targeted by the end of 2026. Moreover, to address HBM (High-Bandwidth Memory) challenges, Intel has unveiled a patented new XBM (eXtended Bandwidth Memory) architecture. This innovative design eliminates the need for expensive silicon interposers by utilizing a backend-transistor DRAM stack with UCIe (Universal Chiplet Interconnect Express) links and built-in repair capabilities, signaling Intel’s multi-pronged approach to resolving the AI memory bottleneck.

Technical / Clinical Details

EMIB-T is Intel’s proprietary technology designed to efficiently connect multiple chiplets on a relatively large substrate. Unlike CoWoS, which relies on a silicon interposer, EMIB uses embedded bridge dies to achieve high-speed inter-die connectivity. This approach has the potential to deliver comparable high-performance packaging while reducing the manufacturing complexity and cost associated with CoWoS. Validation at a 36/35 µm bump pitch is currently underway, catering to the high-density interconnection requirements of next-generation AI chips. Intel Foundry is reportedly booking packaging for over 3 million Tensor Processing Units (TPUs) in 2028, and EMIB technology is being tested for HBM integration.

Meanwhile, Intel’s patented XBM memory architecture aims to resolve the inherent challenges of traditional HBM, particularly the high cost and manufacturing complexity of silicon interposers. XBM employs a backend-transistor (BET) DRAM stack that connects directly to the processor via UCIe interconnects. This design directly stacks DRAM dies onto the logic chip, using fine copper-to-copper bonds or other direct bonding technologies, thereby eliminating the need for a silicon interposer. Furthermore, XBM incorporates built-in repair capabilities, which can efficiently bypass defective cells within the DRAM stack, potentially improving manufacturing yields and reducing overall costs. Concurrently, Samsung is also actively researching HBM thermals, comparing thermo-compression bonding (TCB) and hybrid copper bonding (HCB), with HCB demonstrating significant potential for reducing thermal resistance.

Background & Context

The explosive growth of AI has created new challenges and opportunities for the semiconductor industry. The supply of high-performance AI chips is increasingly dependent not only on the logic performance of CPUs and GPUs but also on HBM availability and advanced packaging technologies. While TSMC’s CoWoS has established itself as a primary packaging solution for AI accelerators, its capacity is constrained, prompting competitors like Intel and Samsung to develop alternative technologies. Intel, benefiting from U.S. government initiatives to strengthen domestic semiconductor manufacturing, is positioning EMIB-T as a strong alternative to CoWoS, aiming to expand its market share through its Intel Foundry ecosystem. The development of innovative memory architectures like XBM is designed to fundamentally address the HBM supply bottleneck and increase flexibility in future AI chip designs. This signifies that technological innovation in the AI era is progressing across all layers of semiconductor design and manufacturing.

Strategic Significance & Outlook

If Intel’s EMIB-T technology receives certification by the end of 2026 and is widely adopted for HBM integration, Intel’s competitiveness in the AI accelerator market will significantly increase. EMIB-T could become an attractive option for customers seeking to bolster packaging capabilities, especially within the U.S. Meanwhile, the XBM architecture holds great promise as a long-term solution to the AI memory bottleneck. Reducing the reliance on silicon interposers could lead to cost efficiencies and simplified manufacturing processes, potentially accelerating the proliferation of AI chips. Moving forward, Intel is expected to integrate both EMIB-T and XBM technologies to offer comprehensive AI hardware solutions, thereby strengthening its presence in the AI market. Samsung’s research into HBM thermal management will also be a critical factor influencing the direction of future HBM technology. These developments clearly demonstrate that packaging and memory, alongside process node miniaturization, are strategically crucial areas in AI chip design.

Source: https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQH8cjA4nUA8BCaIT3NwKTi5yHlHpjol5SEWzWSGVq7aNScbT6PLKg9yuckrOFUxS3V1O3cVEXup3MejY_l1wBzkDhUjtteF1u7XjrddfS0OqOZXIRyUymC4PXu_FGVh3vF41JpigQZNeG4Dt6gFJXdBk-mv7HIFHEr5pc5i5KM97-_8AXfxYpdGDLbBpcmkC9hcgQK-4ek3DzoxApGuCst0lsq5b5wcxGvCFf_z5vhzjU3wcrm5drqZ2sXI4VzG7nMrXHbdO9gqYzLW-TgQKOeX0RFp3nZYX0wEK03JQgW2GP7DI4rcry-OUskuctFHI8NygthpQAdvhJZfEfHo91r57uvbSy9UP7C9JGESibWnvSOr0vfIsGc9T6jG-WdtaWy_1Cc920AqitG2Soab1P_dOGA==

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