TSMC’s CoWoS Bottleneck Threatens to Delay Google TPU Mass Production to 2027

専門メディア Taiwan

Overview

Chronic shortages in TSMC’s CoWoS advanced packaging capacity are projected to delay mass production of Google’s custom AI chips (TPU) until 2027. Despite TSMC’s aggressive expansion plans targeting 120,000 wafers/month by late 2026 and 140,000 by late 2027, Apple’s reservation of initial 2026 capacity leaves limited bandwidth for Google, highlighting the intense competition for critical packaging resources in the AI market.

In Depth

Background

The burgeoning demand for artificial intelligence (AI) has spurred major technology companies like Google to develop specialized AI accelerators, such as their Tensor Processing Units (TPUs). These high-performance chips necessitate sophisticated packaging technologies like CoWoS (Chip on Wafer on Substrate) to integrate multiple logic dies with high-bandwidth memory (HBM), ensuring maximum computational efficiency. However, the unprecedented surge in AI chip demand has strained the supply of these advanced packaging solutions, creating a significant bottleneck in the semiconductor supply chain.

Key Findings / Results

Industry analysis indicates that TSMC’s constrained CoWoS packaging capacity may defer the mass production of Google’s custom AI chip, the TPU, until 2027. TSMC is actively expanding its CoWoS capacity, aiming for 120,000 wafers per month by the end of 2026 and 140,000 wafers per month by the end of 2027, a substantial increase from 45,000 wafers/month in early 2025. Nevertheless, Apple is reportedly securing a significant portion of TSMC’s early 2026 CoWoS capacity for its next-generation processors, consequently limiting the availability for Google’s TPUs. This allocation strategy is expected to cap Google’s TPU production at 3.1-3.2 million units in 2026, with a projected increase to 5-6 million units in 2027. The current demand for CoWoS significantly outstrips supply, impacting major customers and their product timelines.

Technical Significance & Outlook

The CoWoS capacity bottleneck underscores the critical role of advanced packaging in the AI era. As a 2.5D integration technology, CoWoS facilitates high-density integration of logic and memory, a cornerstone for high-performance AI accelerators. The delay in TPU mass production due to packaging constraints highlights that advanced packaging, rather than frontend wafer fabrication, has become a key determinant for AI product time-to-market. TSMC’s aggressive capacity ramp-up, while necessary, reveals the structural challenges in meeting exploding AI demand. The anticipated easing of CoWoS supply in 2027, driven by TSMC’s investments, is expected to benefit not only Google but also other major clients like Broadcom and MediaTek, enabling broader deployment of advanced AI hardware. This situation also prompts hyper-scalers to potentially explore diversified supply chains or alternative packaging solutions to mitigate future single-vendor dependencies.