Japan’s Rapidus and LSTC Launch Optoelectronic Advanced Packaging Project to Cut AI Chip Power Consumption

creating nano technologies inc. (via Digitimes) Japan

Overview

Japan’s next-generation semiconductor manufacturer Rapidus, in collaboration with the Leading-edge Semiconductor Technology Center (LSTC) and other institutions, has initiated an advanced packaging project focused on optoelectronic integration around the Rapidus factory in Chitose, Hokkaido. This endeavor aims to significantly reduce AI chip power consumption by introducing optical technology for inter-chiplet data connections. Development commenced in April 2026, accelerating the convergence of semiconductor design and advanced packaging to address critical power challenges in the AI era.

In Depth

Background: Power Consumption Challenges in the AI Era and the Promise of Optoelectronic Integration

Modern AI chips, particularly those processing large language models and complex inference tasks, demand immense computational power, which translates into substantial energy consumption. Traditional inter-chip connections relying on electrical signals face inherent limitations in data transfer speeds and significant power losses, severely hindering the overall efficiency of AI systems. To overcome these challenges, the semiconductor industry is increasingly looking towards optoelectronic integration (photonic integration) as a next-generation solution for data transmission between chips. Optical signals offer distinct advantages over electrical signals, including higher speeds and significantly lower power dissipation over longer distances.

Rapidus and LSTC Pioneer Optoelectronic Integration Project

Japan’s emerging advanced semiconductor foundry, Rapidus, in conjunction with the Leading-edge Semiconductor Technology Center (LSTC) and associated organizations, has launched an advanced packaging project focused on optoelectronic integration near its factory in Chitose, Hokkaido. The core objective of this project is to drastically reduce AI chip power consumption by introducing optical technology for connecting individual chiplets (smaller semiconductor dies that collectively form a larger chip). This approach aims to circumvent the power overhead typically associated with electrical inter-chiplet communication.

• Objective: To reduce power consumption and enhance the performance of AI chips.
• Technological Approach: Combining chiplet technology with optoelectronic integrated packaging to enable optical data transmission.
• Collaboration: The project involves Rapidus’s 2nm process development in synergy with LSTC and other collaborating institutions.
• Launch: Development officially commenced in April 2026.

This initiative seeks to achieve breakthroughs in the design and manufacturing of next-generation AI chips by closely integrating cutting-edge process technology with advanced packaging. Its alignment with Rapidus’s 2nm process development is expected to yield optimal integration of logic chips and optoelectronic packaging, pushing the boundaries of what is possible in semiconductor performance and efficiency.

Industry Impact and Future Outlook

The optoelectronic advanced packaging project led by Rapidus and LSTC holds immense significance for the Japanese semiconductor industry, particularly in enhancing its global competitiveness. Successful commercialization of this technology could not only dramatically reduce AI chip power consumption but also significantly boost data transfer speeds, paving the way for more powerful and energy-efficient AI systems. This would directly translate into reduced power costs for data centers, lower environmental impact, and the creation of new AI applications. The project is poised to elevate Japan’s presence in advanced semiconductor manufacturing and potentially provide foundational technologies to support the future AI-driven society.