NVIDIA’s Rubin Ultra Architecture Propels Co-Packaged Optics into Production for Gigawatt-Scale AI

Radiant Blog USA

Overview

NVIDIA’s Vera Rubin Ultra architecture, unveiled at GTC 2026, marks the pivotal shift of Co-Packaged Optics (CPO) from conceptualization to an essential production technology for gigawatt-scale AI deployments. CPO directly integrates photonic and electronic integrated circuits onto the switch ASIC package, effectively eliminating electrical trace bottlenecks that limit performance at 1.6 Tb/s to 3.2 Tb/s per port. The Rubin Ultra leverages CPO for out-of-rack connections, with the future Feynman generation (2028) targeting native optical NVLink scaling across the entire system, potentially replacing copper even for short-reach intra-rack communication.

In Depth

Background: The Escalating Demands of Gigawatt-Scale AI

The relentless expansion of AI models and workloads has led to an exponential increase in data center power consumption and interconnect bandwidth requirements. At data rates reaching 1.6 Tb/s and beyond, the electrical traces on printed circuit boards (PCBs) become significant bottlenecks, leading to increased power dissipation, signal integrity issues, and latency. To sustain the growth of AI superclusters, which are rapidly approaching gigawatt power envelopes, a fundamental change in interconnect technology is imperative.

Key Findings: CPO’s Central Role in NVIDIA’s Rubin Ultra Architecture

NVIDIA’s Vera Rubin Ultra architecture, a highlight of GTC 2026, formally introduces Co-Packaged Optics (CPO) as a cornerstone technology for next-generation AI networking. This move signifies CPO’s transition from a theoretical ideal to a production-ready necessity. The technical innovations central to this shift include:

• Direct Photonic-Electronic Integration: CPO achieves unparalleled efficiency by integrating both photonic and electronic integrated circuits directly onto the switch ASIC package. This drastically reduces the length of the electrical interconnects, minimizing signal loss and power consumption that typically plague high-speed electrical signaling.
• Overcoming High-Speed Bottlenecks: At speeds of 1.6 Tb/s to 3.2 Tb/s per port, the electrical traces on traditional PCBs become a primary limiting factor. CPO’s close integration eliminates these long electrical runs, allowing for higher data rates with superior signal integrity and reduced power consumption.
• CPO for Out-of-Rack Connectivity: The Rubin Ultra architecture strategically deploys CPO for out-of-rack connections, optimizing the crucial links between racks in a large-scale AI cluster. This provides a high-bandwidth, energy-efficient foundation for distributed AI compute.
• Future Vision: Feynman and Native Optical NVLink: Looking ahead to 2028, NVIDIA’s Feynman generation aims to expand CPO integration further by implementing native optical NVLink scaling across the entire system, reaching up to NVL1152. This ambitious plan suggests the potential replacement of copper interconnects even for short-reach intra-rack communication, heralding an ‘all-optical’ era for AI supercomputers.

Technical Significance & Outlook: Powering the Next Generation of AI

The integration of CPO into NVIDIA’s flagship AI architectures like Rubin Ultra and Feynman represents a critical leap forward for the industry. This technology is essential for managing the sheer scale and power requirements of future AI factories. By optimizing interconnects for speed, power, and density, CPO enables the realization of more powerful and sustainable AI compute. This development will not only accelerate AI research and deployment but also pave the way for entirely new classes of AI applications that demand ultra-low latency and massive bandwidth, ranging from scientific discovery to advanced autonomous systems.