AMD Explores Powertech’s FOPLP for Next-Generation Zen 7 CPUs, Eyeing Packaging Diversification

TechPowerUp USA

Overview

AMD is reportedly exploring Powertech Technology’s Fan-Out Panel-Level Packaging (FOPLP) for its upcoming “Zen 7” CPUs, codenamed “Grimlock.” This move signals AMD’s strategic intent to build increasingly complex chiplet configurations and potentially reduce reliance on TSMC for advanced packaging services. The flagship “Grimlock” CCD is speculated to feature 16 cores and, when paired with next-generation 3D V-Cache, could achieve up to 224MB of total L3 cache, leveraging FOPLP’s efficiency for high-performance, cost-effective integration.

In Depth

The Necessity of Advanced Packaging in Next-Generation CPUs

The continuous advancement of CPU performance now relies heavily not only on miniaturization technologies but also on sophisticated packaging techniques. Particularly, the chiplet architecture, actively promoted by AMD, integrates multiple smaller chips (chiplets) within a single package, improving manufacturing yields and enhancing design flexibility. For the forthcoming “Zen 7” architecture CPUs, codenamed “Grimlock,” further performance improvements and functional integration necessitate the adoption of new solutions that push beyond the limits of current packaging technologies. Against this backdrop, AMD is actively exploring various advanced packaging solutions.

Interest in Powertech Technology’s FOPLP Solution

One of the key technologies AMD is reportedly considering is the Fan-Out Panel-Level Packaging (FOPLP) solution provided by Powertech Technology. FOPLP, by utilizing larger, rectangular panels compared to traditional wafer-level packaging, can significantly enhance the manufacturing efficiency and cost-effectiveness of chiplets. This capability could enable AMD to economically produce more complex and higher-performance chiplet configurations. Powertech Technology’s FOPLP solution is expected to demonstrate particular advantages in high-performance CPU packaging, especially where high-density redistribution layers (RDL) are required.

AMD’s Strategic Objectives and Zen 7 CPU Outlook

AMD’s exploration of advanced packaging technologies like FOPLP stems from several strategic objectives. One aim is to efficiently construct even more powerful and complex chiplet configurations for AI and HPC (High-Performance Computing) applications. Another key objective is to potentially reduce its reliance on TSMC for advanced packaging services, thereby diversifying its supply chain. TSMC currently faces high demand for advanced packaging, such as CoWoS, which can lead to supply constraints. By expanding its own packaging options, AMD aims to secure future production capacity and flexibility.

The flagship “Grimlock” CCD of the next-generation “Zen 7” architecture is speculated to feature 16 cores. When combined with next-generation 3D V-Cache technology, the total L3 cache capacity could reach up to 224MB. Such large cache capacities are expected to deliver exceptionally high performance in AI workloads and gaming. The potential adoption of Powertech’s FOPLP technology would significantly impact the cost and performance balance of “Grimlock” CPUs, playing a crucial role in AMD’s efforts to establish a competitive advantage in the highly contested CPU market.