TSMC CoWoS Capacity Becomes Major AI Chip Growth Bottleneck: Ramping to 120K Wafers/Month by late 2026 Still Falls Short of Demand

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Overview

TSMC’s CoWoS packaging capacity is identified as the most critical bottleneck hindering AI chip evolution. While TSMC plans to quadruple its CoWoS production capacity from approximately 35,000 wafers/month in late 2024 to 120,000–140,000 wafers/month by late 2026, demand from next-generation architectures like Nvidia’s Blackwell (CoWoS-L) and AMD’s Instinct MI325X is expected to continue outstripping supply. This bottleneck is primarily linked to plasma processing and thin-film deposition, specifically deep reactive ion etching for TSV formation and PVD seed layer deposition/sputtering for RDL, posing a significant supply chain constraint for the AI industry.

In Depth

Key Findings

TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) packaging capacity has emerged as the most critical bottleneck for the production of high-end AI accelerators, effectively slowing down the evolution and market deployment of AI chips. Despite TSMC’s ambitious plans to quadruple its production capacity from approximately 35,000 wafers per month in late 2024 to an estimated 120,000–140,000 wafers per month by the end of 2026, demand from next-generation architectures like Nvidia’s Blackwell (utilizing CoWoS-L) and AMD’s Instinct MI325X is projected to continuously outstrip the available supply.

Technical Details

CoWoS is an indispensable technology for Nvidia’s AI accelerators, which integrate GPU logic dies and HBM (High-Bandwidth Memory) stacks side-by-side on a silicon interposer. The bottlenecks in this packaging process are multifaceted, with plasma processing and thin-film deposition steps being particularly critical. Specifically, deep reactive ion etching (DRIE) for Through-Silicon Via (TSV) formation, and physical vapor deposition (PVD) seed layer deposition and sputtering processes for Redistribution Layer (RDL) creation, are identified as primary contributors to the supply constraints. These processes require advanced technology and extended processing times, thereby limiting the rapid scalability of production capacity.

Background and Context

The explosive growth in demand for high-performance AI chips is intrinsically linked to the rapid expansion of AI infrastructure. However, relying solely on miniaturization, as per traditional Moore’s Law, is increasingly insufficient for achieving desired chip performance gains. Consequently, advanced packaging technologies such as CoWoS, which enable chiplet and 3D integration, have become more crucial differentiators. Nvidia CEO Jensen Huang’s visit to TSMC to secure CoWoS capacity for the Vera Rubin platform underscores the severity of this bottleneck. While TSMC is establishing geographically diversified manufacturing sites in Arizona, Kumamoto (JASM), and Dresden, Germany (ESMC), equipment lead times and process qualification present significant hurdles to rapid capacity expansion.

Strategic Significance and Outlook

The CoWoS capacity shortage is expected to persist, with demand outstripping supply through 2025 and into 2026, a forecast reinforced by predictions at Computex 2026 that AI memory shortages will extend until 2030. This situation has prompted massive capital expenditures across the industry, such as AMD’s commitment of over $10 billion to Taiwan’s ecosystem for AI infrastructure and advanced packaging manufacturing. While TSMC anticipates CoWoS capacity to grow at an 80% annual rate through 2027, hyperscaler demand is still projected to exceed this expansion, indicating that the pace of AI industry growth will remain highly dependent on the timely scaling of CoWoS supply.