Semiconductor Back-End Weekly Report May 7, 2026

IEEE ECTC 2026 Program Reveals Latest Research in Advanced Packaging, Including 3D Integration, Hybrid Bonding, and New Substrate Materials

Tsinghua University Develops 3D Chip Design Tool Tailored for Huawei’s ‘LogicFolding’ Architecture

Singapore Semiconductor Testing Equipment Market Projected to Reach $310 Million by 2033, Growing at 7.8% CAGR

IEEE ECTC 2026 Highlights Packaging Technologies Redefining AI and HPC Scalability Limits

Cadence and Samsung Foundry Deepen 2nm and 3D-IC Collaboration to Meet Surging AI Infrastructure Demand

Synopsys Enhances Power and Performance for AI and Multi-Die Designs on Latest Samsung Foundry Processes

Samsung Reportedly to Launch Physical AI Chiplet Platform Next Year, Accelerating AI Inference and Infrastructure

Fraunhofer IPMS Develops High-Density Chiplet Systems at Wafer Level, Advancing Integration for AI and HPC