IEEE ECTC 2026 Highlights Packaging Technologies Redefining AI and HPC Scalability Limits

IEEE Electronic Components and Technology Conference (ECTC) USA

Overview

The 2026 IEEE Electronic Components and Technology Conference (ECTC) spotlighted packaging technologies redefining AI and HPC scalability limits. Intel Foundry’s R&D emphasized glass core substrates as key to enabling high-performance heterogeneous integration, improved power delivery, stability, and low warpage in large AI/HPC packages. Advancements in EMIB-T technology were also presented, achieving over 12 Gb/s for HBM4e and 64 Gb/s for UCIe interfaces, facilitating complex chiplet-based AI systems. The conference showcased diverse research in 3D integration, hybrid bonding, and new substrate materials.

In Depth

Key Findings

The 2026 IEEE Electronic Components and Technology Conference (ECTC) prominently featured advanced packaging technologies that are redefining the scalability limits of artificial intelligence (AI) and high-performance computing (HPC). Notably, Intel Foundry’s research and development highlighted glass core substrates as a critical enabler for addressing these challenges, showcasing their potential to achieve high-performance heterogeneous integration, improved power delivery and stability, and reduced warpage in large-scale AI and HPC packages.

Technical Details

The conference presented advancements in through-glass via (TGV) technology for glass core substrates as a next-generation foundational technology enabling electrical and optical integration on a single platform. This is expected to significantly reduce energy loss in data transmission within AI chips and dramatically alleviate data movement bottlenecks. Furthermore, Intel announced progress in its EMIB-T (Embedded Multi-die Interconnect Bridge with Through-Silicon Vias) advanced packaging technology. EMIB-T allows for ultra-large, high-performance chiplet systems that scale beyond the limits of silicon reticles and conventional packaging constraints, achieving over 12 Gb/s for HBM4e and 64 Gb/s for UCIe (Universal Chiplet Interconnect Express) interfaces. This technology delivers high bandwidth and low latency in complex AI systems that integrate multiple chiplets.

Background and Context

The explosive growth of AI is imposing unprecedented demands on semiconductor packaging technologies. As the limitations of traditional 2D scaling become apparent, advanced packaging techniques such as 3D integration, chiplets, hybrid bonding, and novel substrate materials have become indispensable for enhancing chip performance and optimizing power efficiency. With TSMC’s CoWoS capacity being a major bottleneck for the AI hardware stack, technologies like glass core substrates and EMIB-T are anticipated as crucial solutions to mitigate this bottleneck and support the continuous evolution of AI infrastructure.

Strategic Significance and Outlook

The research presented at ECTC 2026 holds immense potential for substantially improving the scalability and performance of AI and HPC. The commercialization of glass core substrates and the widespread adoption of advanced packaging technologies like EMIB-T are poised to revolutionize the design and manufacturing of AI chips, enabling the development of higher-performance and more energy-efficient AI processors. These technologies will enhance the performance and efficiency of a wide range of AI applications, from data centers to edge devices, fostering further adoption and evolution of AI technology. ECTC continues to present critical technological trends that shape the future of the semiconductor industry.