Cadence and Samsung Foundry Deepen 2nm and 3D-IC Collaboration to Meet Surging AI Infrastructure Demand

Chiplet News USA

Overview

Cadence and Samsung Foundry are deepening their collaboration in 2nm process technology and 3D-IC (3D Stacked Integrated Circuit) technology to address the surging demand for AI infrastructure and physical AI. This partnership aims to accelerate high-performance computing solutions for next-generation AI systems, providing a design environment that maximizes Samsung’s advanced packaging and chiplet platform capabilities. The technological integration is expected to enhance AI chip performance and energy efficiency while shortening time-to-market.

In Depth

Key Findings

Cadence and Samsung Foundry are strengthening their collaboration in 2nm process technology and 3D-IC (3-Dimensional Stacked Integrated Circuit) technology to address the rapidly escalating demand for artificial intelligence (AI) infrastructure and physical AI. This strategic partnership aims to accelerate high-performance computing solutions for next-generation AI systems and reduce time-to-market.

Technical Details

Cadence provides optimized Electronic Design Automation (EDA) tools and Intellectual Property (IP) for Samsung Foundry’s advanced processes, specifically tackling design challenges at the 2nm process node. This collaboration delivers solutions that manage the complexity of AI chip and multi-die system designs, optimizing power consumption while maximizing performance. 3D-IC technology vertically stacks multiple dies, shortening interconnect distances between chips, improving data transfer speeds, and enhancing power efficiency. The synergy between Samsung Foundry’s advanced packaging technologies, such as 2.xD Cube Packaging, and Cadence’s EDA toolchain is expected to facilitate seamless heterogeneous integration and dramatically boost the overall performance of AI systems.

Background and Context

The explosive growth of AI presents unprecedented design and manufacturing challenges for the semiconductor industry. As the limits of traditional 2D scaling approach, chiplet technology and 3D stacking are becoming indispensable for achieving the immense computational power, high bandwidth, and low power consumption required by AI workloads. Samsung is striving to achieve system-level co-optimization within an integrated development framework that combines advanced logic, memory, and packaging, with its collaboration with Cadence being a crucial part of this strategy. Synopsys is also partnering with Samsung Foundry to provide solutions that improve power and performance for AI and multi-die designs, indicating that close collaboration between EDA vendors and foundries is essential for resolving industry bottlenecks.

Strategic Significance and Outlook

The deepened collaboration between Cadence and Samsung Foundry is critical for accelerating technological innovation in the AI and HPC markets. This partnership streamlines the design and manufacturing processes for AI chips, enabling the rapid development of higher-performance and more energy-efficient AI processors. By strengthening the design ecosystem for next-generation AI systems, both companies are expected to support the continuous evolution of AI infrastructure and play a central role in shaping a future where physical AI becomes pervasive in applications like autonomous driving, robotics, and smart cities.