Key Findings
TSMC is significantly accelerating the development of CoPoS (Chip-on-Panel-on-Substrate) packaging, a next-generation technology intended to eventually supersede CoWoS (Chip-on-Wafer-on-Substrate). This innovative approach centers on glass core substrates, co-developed with Ibiden and Innolux. It aims to achieve a remarkable 30% cost reduction and boost wafer utilization from under 70% to over 90% for ultra-large AI chips post-2028, effectively addressing geometric waste challenges inherent in current processes.
Technical Details
CoPoS packaging differs from traditional wafer-level CoWoS by integrating chips at the panel level. The glass core substrate forms a crucial tri-layer design, sandwiched by Ajinomoto Build-up Film (ABF) material. TSMC’s validation metrics for glass substrates reveal significant advantages over organic substrates, including superior co-planarity, a substantially lower coefficient of thermal expansion (CTE), and enhanced power integrity. These improvements are vital for large AI GPU packages, as they drastically reduce issues like warpage and thermal stress, allowing for the integration of more chips with higher reliability. The leap in wafer utilization from below 70% to over 90% will profoundly resolve the problem of geometric waste (e.g., mismatch between circular wafers and square chips) during the manufacturing of ultra-large chips, directly translating to substantial cost reductions.
Background & Context
As AI continues to evolve, the size and complexity of AI chips are steadily increasing. While advanced packaging technologies like CoWoS have become increasingly critical, they have also exposed the physical limitations of organic substrates—particularly warpage and thermal expansion issues at larger scales—and challenges with cost efficiency in wafer-level manufacturing. To overcome these hurdles, TSMC is spearheading the adoption of glass substrates, forging strategic collaborations with leading ABF substrate manufacturer Ibiden of Japan and display panel maker Innolux of Taiwan. This industry shift clearly indicates a move beyond mere transistor scaling towards innovation in back-end processes to pursue both performance and cost efficiency.
Strategic Significance & Outlook
The adoption of CoPoS packaging and glass core substrate technology has the potential to revolutionize the design and manufacturing of next-generation AI chips, especially large-scale AI processors, from 2028 onwards. The projected cost reductions and utilization improvements will accelerate the proliferation of AI hardware, contributing to the realization of a wider array of AI applications. This technology is expected to reshape the competitive landscape of the entire semiconductor industry, creating new business opportunities for material suppliers and packaging equipment manufacturers. TSMC’s focus on CoPoS is a critical trend that will significantly influence the future direction of advanced packaging technology and is keenly watched by the industry.
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