NVIDIA to Boost CoWoS Production Capacity by 3.5x to Over 120,000 Wafers/Month by End-2026, Securing HBM4 Supply

September 13, 2026

SemiconductorX USA

Overview

NVIDIA plans to scale its CoWoS (Chip-on-Wafer-on-Substrate) production capacity by 3.5x to 120,000–130,000 wafers per month by the end of 2026, up from 35,000, driven largely by its own demand. The company is set to consume approximately 60% of TSMC’s total CoWoS allocation in 2026, with HBM4 supplied by SK Hynix (70%) and Samsung (30%). Furthermore, NVIDIA is co-developing CoWoP (Chip on Wafer on PCB) with SPIL to eliminate substrate layers, aiming for improved efficiency and cost reduction in AI semiconductor supply chains.

In Depth

Key Findings: NVIDIA Massively Expands CoWoS Capacity and Solidifies HBM4 Supply Chain

NVIDIA is aggressively pursuing a plan to expand its CoWoS (Chip-on-Wafer-on-Substrate) packaging production capacity by approximately 3.5 times, from its current 35,000 wafers per month to 120,000–130,000 wafers per month by the end of 2026. This monumental expansion is predominantly driven by NVIDIA’s own escalating demand for AI GPUs, underscoring a critical strategy to stabilize the supply of HBM4 memory and GPUs essential for its next-generation AI platforms.

Technical & Supply Chain Details: CoWoS Allocation and HBM4 Supplier Strategy

Dramatic CoWoS Capacity Increase: NVIDIA is projected to consume roughly 60% of TSMC’s total CoWoS production capacity in 2026, a testament to its dominant position in the AI chip market. This significant scale-up is expected to alleviate the packaging bottleneck that has historically constrained AI accelerator production.
Diversified HBM4 Supply: To ensure a robust and stable supply of high-bandwidth memory (HBM4), NVIDIA will source approximately 70% from SK Hynix and 30% from Samsung. This diversified approach mitigates the risk of over-reliance on a single supplier.
CoWoP Technology Development: In collaboration with SPIL (part of the ASE Group), NVIDIA is advancing a novel packaging technology known as CoWoP (Chip on Wafer on PCB). This innovation aims to eliminate the intermediate substrate layer used in traditional CoWoS, potentially reducing packaging complexity, lowering costs, decreasing latency, and enabling further miniaturization.

Background & Industry Context: AI Demand and Supply Chain Pressure

The proliferation and sophistication of AI models have driven an unprecedented demand for high-performance GPUs, along with their associated HBM and advanced packaging technologies. Specifically, 2.5D packaging solutions like CoWoS are indispensable for integrating GPUs and HBM, and their limited production capacity has long been a bottleneck for AI chip supply. NVIDIA’s announcement signifies a proactive strategic investment to address this bottleneck and accommodate future market growth.

Strategic Significance & Outlook: Intensifying AI Semiconductor Competition and NVIDIA’s Lead

NVIDIA’s substantial increase in CoWoS capacity and investment in innovative packaging technologies like CoWoP will further solidify its competitive advantage in the AI semiconductor market. The ability to rapidly bring more AI GPUs to market could widen its lead over rivals. Should CoWoP technology achieve practical implementation, it promises reductions in packaging costs and performance enhancements, profoundly impacting the overall economics of AI hardware.

Source: https://semiconductorx.com/spotlight-nvidia.html

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