Rapidus Explores Panel-Level Packaging on Glass Substrates for Next-Gen AI/HPC Processors

Tom’s Hardware Japan

Overview

Japanese semiconductor firm Rapidus is actively exploring the adoption of panel-level packaging (PLP) on large 600mm x 600mm glass panels for manufacturing high-end multi-chiplet processors designed for AI and HPC accelerators. This technology offers significant advantages over silicon interposers and organic core substrates, aiming to leapfrog competitors in next-generation advanced packaging. Rapidus plans to discuss this initiative at SEMICON Japan, highlighting Japan’s push for global leadership in advanced semiconductor manufacturing.

In Depth

Background: The Evolution of Advanced Packaging and Material Selection

Modern AI and High-Performance Computing (HPC) processors necessitate heterogeneous integration, where multiple chiplets (small semiconductor dies with specific functionalities) are integrated at high densities. Such designs demand advanced packaging technologies that enable fast and efficient inter-chiplet connections. While silicon interposers and organic core substrates have been primary solutions, the increasing size and performance requirements of AI chips have introduced new challenges regarding thermal management, signal transmission speed, manufacturing cost, and overall fabrication size. Specifically, the limitations of existing technologies are becoming apparent in packaging larger and more complex AI accelerators.

Rapidus’s Exploration of Panel-Level Packaging on Glass Substrates

Rapidus, Japan’s next-generation semiconductor foundry, is actively exploring panel-level packaging (PLP) on glass substrates as an advanced packaging solution to overcome these challenges and potentially surpass competitors. The core of this innovative approach lies in utilizing large 600mm x 600mm glass panels as substrates, significantly larger than current wafer sizes. Glass substrates offer notable advantages over traditional materials:

• Superior Thermal and Mechanical Stability: Glass possesses higher rigidity and thermal stability compared to organic substrates, drastically reducing warpage that typically occurs when integrating large dies or multiple chiplets. This leads to higher yields and enhanced reliability.
• Low Dielectric Loss and High-Density Interconnects: Glass has low dielectric loss, minimizing electrical signal degradation and enabling high-speed data transmission. Its exceptionally flat surface is also ideal for forming ultra-fine redistribution layers (RDLs), facilitating high-density interconnections.
• Improved Cost Efficiency: Manufacturing on large panel sizes allows for a greater number of chiplets to be processed simultaneously, potentially reducing manufacturing costs. This offers significant economic benefits, particularly for the mass production of high-end multi-chiplet processors.

Rapidus intends to discuss its PLP on glass substrate initiatives at industry events like SEMICON Japan, sharing its technical vision. This endeavor underscores Japan’s strong resolve to establish global leadership in the advanced packaging sector.

Industry Impact and Future Outlook

The realization of PLP on glass substrates by Rapidus has the potential to fundamentally transform the performance and cost efficiency of AI and HPC processors. If successfully established, this technology could resolve current packaging bottlenecks and enable the design and manufacturing of even more complex and higher-performing AI accelerators. Coupled with Japan’s leading 2nm process technology, Rapidus could secure a unique competitive advantage in the global market. PLP on glass substrates is expected to be a foundational technology for next-generation semiconductor manufacturing, significantly contributing to the efficiency of data centers, the creation of new AI applications, and the realization of a sustainable digital society.