Background: AI Boom and the Criticality of Semiconductor Packaging
The rapid advancement of AI technology has brought unprecedented demands and innovation imperatives to the semiconductor industry. Specifically, AI chips essential for Large Language Models (LLMs) and High-Performance Computing (HPC) cannot be realized without advanced packaging technologies such as High Bandwidth Memory (HBM) and Chip-on-Wafer-on-Substrate (CoWoS). These technologies are crucial for dramatically enhancing inter-chip data transfer speeds and improving power efficiency. ASMPT, as a leading provider of semiconductor manufacturing equipment and solutions, is accelerating strategic moves to address the challenges and opportunities of the AI era.
Key Findings: Purpose and Role of the Technical Advisory Council (TAC)
The Technical Advisory Council (TAC) established by ASMPT will play a vital role in driving innovation in the AI era. The primary objectives and functions of the TAC are as follows:
- Supporting Advanced Packaging Roadmap Development: The TAC will provide strategic guidance on the roadmap for 3.5D and 2.5D packaging, including HBM and CoWoS, as well as future advanced packaging technologies. This is critically important for defining the direction of next-generation packaging solutions essential for improving AI chip performance and cost efficiency. It will also serve as a forum to consider alternative technologies and optimization strategies in response to challenges like the CoWoS supply constraints noted by Tom’s Hardware.
- AI-Enabling Interconnect Solutions: High-performance AI chips require high-speed, reliable interconnects at the chip-to-chip, board-to-board, and even system levels for efficient data flow. The TAC will lead the evolution of these interconnect technologies and identify solutions to resolve bottlenecks.
- Fostering Ecosystem Collaboration: The TAC will provide strategic insights to strengthen cooperative relationships across the entire semiconductor ecosystem (chip designers, foundries, packaging suppliers, material vendors, etc.). This is indispensable for sharing technical standards, collaborative R&D, and optimizing supply chains, given the complexity of AI development.
- Understanding Technology Trends and Market Demand: The TAC will deeply understand the latest AI technology trends, particularly market demands and challenges in areas like LLM evolution (e.g., the release of Claude Opus 4.8) and embodied AI (e.g., X-Square Robot’s WALL-WM), and integrate these insights into ASMPT’s product development and solution offerings.
Technical Significance & Outlook: ASMPT’s Market Positioning and Contribution to AI Infrastructure
ASMPT’s formation of a Technical Advisory Council signals its intent to strengthen its role as a strategic partner beyond just an equipment supplier within the AI-era semiconductor manufacturing ecosystem. The insights and guidance gained through the TAC will enable ASMPT to develop and deliver innovative packaging and interconnect solutions that maximize AI chip performance. This will contribute to improving the overall efficiency and scalability of AI infrastructure and indirectly help address challenges such as data center power consumption (as highlighted by Computer Weekly). In the long term, this initiative is expected to foster co-design between AI hardware and software, contributing to a future where more sustainable and high-performing AI systems are built. ASMPT’s TAC will serve as a symbol of a collaborative approach to ensure the semiconductor industry remains at the forefront of the AI revolution.
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