New Technology– category –
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SK hynix Ships 12-Layer HBM4E Samples with Advanced MR-MUF Packaging, Achieving Over 20% Power Efficiency and 17% Thermal Resistance Improvement Over HBM4
Advanced Packaging News South Korea Overview SK hynix announced the sampling of its 12-layer HBM4E memory for next-generation AI systems, leveraging proprietary Advanced MR-MUF packaging. This innovation delivers 48GB capacity per stack ... -
Semiconductor Startup Funding Diversifies Beyond AI Accelerators to Interconnects and Packaging; TSMC CoWoS Capacity to Quadruple by EOY 2026
New Market Pitch Global Overview Semiconductor startups attracted $8.4 billion in Q1 2026, pushing cumulative funding to $10.7 billion, with investments diversifying beyond AI accelerators to interconnects, optical I/O, memory, and advan... -
ASML, TSMC, and Imec Achieve Breakthrough 300mm Integration for Industry-Ready 2D-Material Transistors
The cleanroom Portal - Reinraum Online Germany Overview Imec, in collaboration with ASML and TSMC, presented a robust and scalable 300mm integration approach for n- and p-FETs based on 2D materials at the IEEE/JSAP Symposium 2026. This b... -
Imec’s Chiplet Imperative: Analyzing the Transition to High-Bandwidth, Low-Energy AI/HPC Systems
imec ベルギー Overview Imec has published a comprehensive analysis identifying the economic and technical inflection points for transitioning from monolithic ASICs to chiplet-based designs, particularly for AI, HPC, and data center appli... -
Imec Unveils Vertically Stacked IGZO FeFETs, Revolutionizing AI Memory Density and Efficiency
IN Electronics & Design ベルギー Overview Imec has achieved a significant breakthrough in ferroelectric memory for AI systems, demonstrating a vertically stacked FeFET architecture utilizing IGZO and successfully reducing ferroelectric c... -
Imec Targets Optical Interconnect Packaging Bottlenecks for Next-Gen AI and HPC
ApplyKite (imec) ベルギー Overview Imec is seeking a PhD candidate for groundbreaking research into microfluidics and photonics packaging, crucial for optical interconnects in future AI and High-Performance Computing (HPC) systems. The p... -
TSMC’s CoWoS Packaging Capacity Identified as Bottleneck in Korea’s HBM4E Race, Despite SK hynix and Samsung Shipments
Aju Press South Korea Overview Despite SK hynix and Samsung Electronics commencing sample shipments of 12-layer HBM4E chips to major customers like Nvidia, TSMC's CoWoS advanced packaging capacity is highlighted as the true bottleneck in... -
Samsung Validates Hybrid Copper Bonding’s Superior Thermal Management for HBM4E, Outperforming TCB
ET News (via IEEE paper) South Korea Overview Samsung published research in IEEE demonstrating that its Hybrid Copper Bonding (HCB) offers significant thermal management advantages over conventional Thermo-Compression Bonding (TCB) for H... -
ATLANT 3D, A*STAR IMRE, and NAMIC Launch AI-Driven Materials Development Hub in Singapore
PR Newswire Singapore Overview ATLANT 3D, A*STAR IMRE, and NAMIC have signed an MoU to establish an Advanced Materials Development Hub (A-HUB) in Singapore, leveraging ATLANT 3D's Direct Atomic Layer Processing (DALP®) technology. This c... -
TSMC Boosts CoWoS Capacity, Reducing AI Chip Supply Gap to 10% by Late 2026; Next-Gen CoPoS Pilot Production for NVIDIA’s ‘Feynman’ Slated for 2027
Futuretech Components / Daily Beirut Taiwan Overview TSMC is rapidly expanding its CoWoS advanced packaging capacity to meet surging demand from AI accelerators and HPC applications, projected to narrow the supply-demand gap from 20% to ...
