TECHNOLOGY EXPLAINER
What an Interconnect Is
— change the distance and you change the link, and the materials with it
A single bit travels across seven orders of magnitude: from a few micrometres of wiring inside a chip to several metres of optical fibre between machines. Along the way the conductor, the insulator and the physics that decides performance are all swapped out. Interconnect is the word for that whole hierarchy.
- What an interconnect is (the short version)
- A map of the hierarchy — seven orders of magnitude
- A materials engineer's view (1): what limits you depends on the distance
- Measuring by density — pitch counts as a square
- TSMC's three pillars — chosen by application
- A materials engineer's view (2): the move to get rid of the bump
- What is still hard
- Glossary / Primary sources / Claim-to-source audit
Sourced = a value stated in published material from a research institute or manufacturer (link given)
Our calculation = a figure this article derived, with the assumptions spelled out
Not yet confirmed = research-stage work with no confirmed production record
Anything beyond those — structural framing and readings of what the materials have to do — is marked as Commentary.
1. What an interconnect is (the short version)
An interconnect is any path a signal travels along, electrical or optical. Where the other articles in this series each take one way of joining things, this one takes the map of the whole thing.
- How far it reaches: from wiring inside the chip to the fibre running between machines
- What changes along the way: distance, cross-section, conductor, insulator, and the cause of loss
- How it is measured: density (how many lines fit), speed, power, and reach
The individual joining methods already have their own articles. This one lines them up as a hierarchy.
- Wires, bumps, solder → the Bonding and Bumps articles
- Direct die-to-die joining → the Hybrid Bonding article
- Wiring inside the package → the Interposer, RDL and Bridge articles
- Wiring in the substrate → the Package Substrate and Via articles
- Going optical → the Co-Packaged Optics article
- Standardisation (UCIe) → the Chiplet article
2. A map of the hierarchy — seven orders of magnitude
Start by laying the distances out side by side.
3. A materials engineer's view (1): what limits you depends on the distance
Call it all "wiring" if you like, but over a short run and over a long run, completely different physics decides how well it performs.
Take the material requirements this series has covered and sort them into these three bands, and they fall into place neatly.
- The very short runs: what is being asked for is joint quality and joint density. The UBM and the intermetallics of the Bumps article, the surface flatness of the Hybrid Bonding article — every one of them is an interface question, not a loss question
- The middle runs: what is being asked for is the dielectric behaviour of the insulator. The Df of the Buildup Film article, the surface roughness of the Via article — this is where permittivity and loss finally take the lead role
- The long runs: give up on electricity and move to materials that carry light: the transmittance, laser durability and refractive-index matching from the CPO article
All of it files under "interconnect materials", yet the properties being demanded belong to different disciplines. That is why a back-end materials supplier ends up with such a broad catalogue (this article's commentary).
4. Measuring by density — pitch counts as a square
Over the short runs, what decided performance was how many lines you could fit. And how many you can fit is set by the pitch of the connection points.
The UCIe Consortium defines a profile for each packaging class. Of UCIe-3D it says the profile is "optimized for hybrid bonding with a bump pitch functional for bump pitches as big as 10-25 microns to as small as 1 micron or less"Sourced.
Lay the connection points out on a grid and the count per unit area goes as the inverse square of the pitchOur calculation.
- Pitch 110 µm (assumed for the UCIe Standard Package) → about 83 per mm²
- Pitch 45 µm (assumed for the UCIe Advanced Package) → about 494 per mm²
- Pitch 10 µm → 10,000 per mm²
- Pitch 1 µm (the floor quoted for UCIe-3D) → 1,000,000 per mm²
110 µm against 1 µm is a factor of 110 in pitch. In density it is 110², roughly 12,100 times.
Assumptions: a plain count for a square lattice packed with no gaps. In practice power and ground allocations, keep-out zones and test pads all intervene, so it never works out this way. The pitch values are the ones UCIe assumes in its profiles.
Halve the pitch and the density is four times higher. For a designer there is no better return on investment. So the pressure to tighten the pitch never lets up.
On the material side, though, halving the pitch does not make life merely four times harder. This series has shown why.
- The Bumps article: as the joint shrinks, the intermetallic fraction rises sharply
- The Underfill article: as the gap narrows, the filler can no longer get in
- The Hybrid Bonding article: the flatness demanded of the surface moves to the nanometre scale
- The Test article: there is nowhere left to land a probe needle
The design side gains as a square; the material side pays more than that. That asymmetry is what keeps back-end materials development under constant pressure (this article's commentary).
5. TSMC's three pillars — chosen by application
TSMC Research organises chip-to-chip interconnect into three pillars: "Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT)."Sourced
Each of them, it says, is tied to an integration technology — CoWoS, InFO and SoIC respectivelySourced.
The criteria TSMC lists are PPACC — Power consumption, Performance, Area (form factor), Cost, Cycle time to marketSourced.
What is worth noticing is that two of the five are not technical performance at all: cost, and time to market.
So the three pillars are not sorted by "which one is best" but by "which one suits which application". The reason the highest-density option, bumpless SoIC, does not simply replace everything else is not that it performs worse, but that for some applications the cost and the lead time do not work.
The conclusion this series keeps arriving at — that materials do not converge on a single answer, seen in the four wire families, in sockets built differently for different jobs, in CUF pulling both hard and soft — comes straight out of the shape of these criteria (this article's commentary).
6. A materials engineer's view (2): the move to get rid of the bump
One of TSMC's three pillars is bumpless bondSourced: make no protrusion at all, and join two flat surfaces directly.
On 2 March 2026 imec described its die-to-wafer (D2W) hybrid bonding as using "direct oxide-to-oxide links between the CMOS die and the package interface" to achieve "ultra-dense, high-bandwidth chip-to-chip links"Sourced.
At the same time it released a PDK for fine-pitch RDL, specified as "line widths and spaces down to 1.3 microns and microbump pitches as tight as 20 microns"Sourced. With it, imec says, a designer can "improve communication speed by up to 40% and reduce energy per bit as much as 15%, on a UCIe-Advanced die-to-die interface"SourcedNot yet confirmed.
Line up the steps this series has followed and the direction is unmistakable.
- Wire: string metal across, one line at a time (the Bonding article)
- Solder bump: a ball that melts and freezes (the Bumps article)
- Copper pillar: cut the solder back to a cap on the tip (the Bumps article)
- Hybrid bonding: drop the solder entirely and join with copper and oxide alone (the Hybrid Bonding article)
- Bumpless: remove the protrusion itself
It is a history of stripping away, step by step, the extra material used to make the connection. And the more you strip away, the harsher the demands on what is left — with no solder there, nothing is absorbing the dimensional scatter any more. The CMP flatness requirement from the Hybrid Bonding article, dishing controlled to nanometres, is the price of that (this article's commentary).
What imec's RDL PDK shows, meanwhile, is that the organic side still has room to get finer: 1.3 µm lines and spaces, 20 µm microbump pitchSourced. That is finer still than the 2/2 µm covered in the Fan-out article. The road that erases the bump and the road that keeps thinning organic material are running in parallel (this article's commentary).
7. What is still hard
(1) There is a conversion cost between the levels
Every time a signal crosses from one level to the next, a conversion happens: chip wiring to bump, bump to substrate trace, substrate to connector, electrical to optical.
As the CPO article showed, NVIDIA describes the conventional route this way: "the data signal must traverse long electrical paths from the switch ASIC to the PCB, connectors and finally into the external transceiver before being converted to an optical signal. This segmented journey incurs substantial electrical loss"Sourced.
"Segmented journey" is the phrase that gets at it. The joins between levels are exactly where the loss is created. So improvement can go one of two ways: cut the number of levels, or move the joins closer together (this article's commentary).
(2) Push electricity further, or go optical sooner
Broadcom's published figures put the optical link power per 800G at 14 W for a pluggable module and 5.5 W for CPOSourced.
All that changed is where the conversion to light happens — moved from metres away to centimetres away. The number of conversions is the same. Only the electrical distance changed, and the power drops by close to sixty per cent (this article's commentary).
(3) The denser it gets, the more the heat piles up
Raising connection density means pushing more signals through the same area. More signals means more power burnt in that area.
TSMC lists "energy efficient computing systems" as a characteristic of SoICSourced precisely because raising density alone does not work: the energy per bit has to come down with it. The heat-removal discussion from the CoWoS and Flip Chip articles is the other face of interconnect density (this article's commentary).
Interconnect is the word that lets you re-sort everything this series has covered onto a single axis.
- The shorter the run: what is asked for is density, and pitch counts as a square
- In the middle: what is asked for is dielectric behaviour — Df and surface roughness
- Over long runs: give up on electricity and move to materials that carry light
And performance is not the only criterion. TSMC's PPACC includes cost and time to marketSourced.
Which is why interconnect technology does not converge on one answer. Silicon interposers, fan-out RDL, bumpless bonding, organic substrates, optics — each keeps a place that suits its distance and its application. For a materials supplier that means not betting on one of them, but holding a different product for each level. That is the shape of this field (this article's commentary).
8. Glossary
- Interconnect
- The general term for the paths a signal travels, in levels running from inside the chip to between machines.
- BEOL
- Back End Of Line. The front-end steps that build the wiring after the transistors are formed.
- Die-to-die (D2D)
- Connecting dies to one another inside the same package.
- Bumpless bond
- Joining two flat surfaces directly, with no protrusion (no bump) formed.
- Hybrid bonding
- Bonding copper and the insulating oxide at the same time (covered in its own article).
- D2W
- Die to Wafer. Bonding singulated dies onto a wafer.
- PPACC
- Power consumption, Performance, Area, Cost, Cycle time to market. The selection criteria TSMC uses.
- UCIe
- Universal Chiplet Interconnect Express. The industry standard for die-to-die links (covered in the Chiplet article).
- UCIe-S / -A / -3D
- The profiles for standard packages, advanced packages and 3D stacking respectively.
- Connection density
- Connection points per unit area. It goes as the inverse square of the pitch.
- Skin effect
- The higher the frequency, the more the current crowds to the conductor surface. The effective cross-section shrinks and resistance rises.
- Dielectric loss (Df)
- The fraction of electrical energy turned into heat inside the insulator (covered in the Buildup Film article).
- pJ/bit
- The energy needed to send one bit. The efficiency metric for an interconnect.
- Bandwidth density
- The data rate that can be carried per unit length or per unit area.
- RDL
- Re-Distribution Layer, the redistribution wiring layer (covered in its own article).
- PDK
- Process Design Kit. The set of rules and models a designer needs in order to use a given manufacturing process.
9. Primary sources
- TSMC Research "Interconnect / Off-chip Interconnect" — research.tsmc.com
- UCIe Consortium "Specifications" — uciexpress.org
- imec "NanoIC opens access to first-ever fine-pitch RDL and D2W hybrid bonding interconnect PDKs", 2 March 2026 — imec-int.com
- NVIDIA "Scaling AI Factories with Co-Packaged Optics for Better Power Efficiency", technical blog — developer.nvidia.com
- Broadcom "TH5 51.2T Bailly CPO (Co-Packaged Optics)", March 2023 (PDF) — docs.broadcom.com
10. Claim-to-source audit
| Claim in the text | Basis | Label |
|---|---|---|
| That "Silicon interposer, high-density fine-pitch fan-out RDL and bumpless bond are the three pillars of chip-to-chip interconnect on innovative advanced heterogeneous integration technologies (HIT)." and that they map to CoWoS, InFO and SoIC respectively. That the silicon interposer offers "high interconnect density, high specific capacitance density, and large reticle size for exascale HPC/AI", fan-out "high interconnect density and large reticle size in fan-out for cost and performance in HPC/network AI", and SoIC "high 3D interconnect density with ultra-low bonding latency for energy efficient computing systems". That PPACC stands for "Power consumption, Performance, Area (form factor), Cost, Cycle time to market" | TSMC Research, "Off-chip Interconnect"[Source 1] https://research.tsmc.com/english/research/interconnect/off-chip-interconnect/publish-time-1.html | Sourced |
| That UCIe 2.0 covers 3D packaging and that "UCIe-3D is optimized for hybrid bonding with a bump pitch functional for bump pitches as big as 10-25 microns to as small as 1 micron or less to provide flexibility and scalability." | UCIe Consortium, "Specifications"[Source 2] https://www.uciexpress.org/specifications | Sourced |
| Announced 2 March 2026. That the fine-pitch RDL PDK covers "line widths and spaces down to 1.3 microns and microbump pitches as tight as 20 microns". That D2W hybrid bonding achieves "ultra-dense, high-bandwidth chip-to-chip links" through "direct oxide-to-oxide links between the CMOS die and the package interface" | imec press release, 2 March 2026[Source 3] https://www.imec-int.com/en/press/nanoic-opens-access-first-ever-fine-pitch-rdl-and-d2w-hybrid-bonding-interconnect-pdks | Sourced |
| That imec's PDK is said to "improve communication speed by up to 40% and reduce energy per bit as much as 15%" on a UCIe-Advanced die-to-die interface. The same release calls it an "exploratory version", and no production record has been confirmed | imec press release, 2 March 2026[Source 3] https://www.imec-int.com/en/press/nanoic-opens-access-first-ever-fine-pitch-rdl-and-d2w-hybrid-bonding-interconnect-pdks | Not yet confirmed |
| That on the conventional route "the data signal must traverse long electrical paths from the switch ASIC to the PCB, connectors and finally into the external transceiver before being converted to an optical signal. This segmented journey incurs substantial electrical loss". That electrical loss goes from "up to 22 dB" to "~4 dB", and power from "often 30W" to "as low as 9W" | NVIDIA technical blog[Source 4] https://developer.nvidia.com/blog/scaling-ai-factories-with-co-packaged-optics-for-better-power-efficiency/ | Sourced |
| That optical link power per 800G is 14 W for a pluggable module and 5.5 W for CPO | Broadcom, "TH5 51.2T Bailly CPO"[Source 5] https://docs.broadcom.com/doc/th5-51.2t-bailly-cpo | Sourced |
| The connection densities obtained as (1000/p)² per mm² for a square lattice of pitch p (110 µm to about 83, 45 µm to about 494, 10 µm to 10,000, 1 µm to 1,000,000), and the density ratio of about 12,100 between 110 µm and 1 µm | Our calculation. A plain count for a square lattice packed with no gaps; power and ground allocation, keep-out zones and test pads are not considered. The pitch values are representative figures taken from the UCIe profile assumptions and company disclosures | Our calculation |
| That the levels in Fig. 1 and their wiring lengths (1 µm to several metres) indicate rough orders of magnitude rather than the specification of any product, and that the division into levels is itself this article's framing | This article's note | Commentary |
| The division of distance into three bands, each limited by the number of connections, by dielectric loss and skin effect, or by electricity not reaching at all, together with the materials mapped to each band. The observation that the design side gains as a square while the material side pays more than that. The reading that because PPACC includes cost and lead time the technology does not converge on one answer. The account of extra joining material being stripped away step by step, and the point that once the solder is gone nothing absorbs dimensional scatter. The framing that the joins between levels are where loss is created, so improvement means fewer levels or closer joins. The reading that only the electrical distance changed. The point that density and heat removal are two faces of the same thing. The mapping in Fig. 5 of TSMC's three pillars onto articles in this series | Commentary by this article based on the published material. Not a position expressed by any of the companies or bodies cited | Commentary |
| That Figs. 1, 2, 4 and 5 are drawings made for explanation rather than real observed images or engineering drawings | This article's note | Commentary |
Last updated 20 September 2026. Sources are limited to primary material (research pages from semiconductor manufacturers, published material from standards bodies, press releases from research institutes, and manufacturers' technical documents). Because the article includes its own framing of the hierarchy and its own reading of what the materials have to do, those parts are marked as Commentary and kept separate from sourced fact. All figures are explanatory concept graphics. Visual-overview figures are shown as AI-generated conceptual images, matching the Japanese edition. Vector drawings are retained where they carry quantitative values or precision-critical technical labels. AI-generated images do not depict real equipment, products, facilities, dimensions or exact cross-sections; replaced source SVG overview drawings remain in the HTML but are hidden.