MENU
Advanced Materials Intelligence
  1. Home
  2. Optical Interconnects and SerDes Explained | Photonics

Optical Interconnects and SerDes Explained | Photonics

Back to Technology, Institution & Company Guides

TECHNOLOGY EXPLAINER

Optical Interconnects and SerDes
— double the speed, and copper reaches only half as far

Most of the signals running between chips still travel over copper wiring. The circuit that sends and receives them is the SerDes (serialiser/deserialiser). When the IEEE Ethernet standard doubled the speed of a lane from 100 Gb/s to 200 Gb/s, the reach objective for copper cable was halved, from 2 m to 1 m. NVIDIA's GB200 NVL72 links its 72 GPUs inside the rack with copper cables. Where light becomes necessary — that boundary is set by the losses in copper and polymer.

Built from primary sources: IEEE 802.3 objectives documents, OIF implementation agreements and announcements, the LPO MSA specification, and NVIDIA's official product pages and technical blog / Last updated September 2026

Conceptual image of many thin silver-jacketed cables bundled in parallel against a dark background, curving gently as they run into the distance
Conceptual image (AI-generated). An impression of the many electrical links that connect chips. It does not show the cables, cable count or structure of any particular product.
What this article covers
  1. What SerDes and optical interconnects are (the short version)
  2. What a SerDes does — parallel to serial, then making sense of a damaged waveform
  3. Why copper loses out at high frequencies
  4. Our calculation: loss budgets lined up as "amplitude left"
  5. Our calculation: what happened when the lane rate doubled
  6. Scale-up networks — NVLink wires the rack in copper
  7. A materials engineer's view (1): the loss budget is spent on resin and copper foil
  8. A materials engineer's view (2): how far copper reaches is a boundary set by materials
  9. What is still hard
  10. Glossary / References / Claim-to-source audit
How claims are labelled in this article

Sourced = stated in a standard, a public document from a standards body, or a company's official announcement (link given)
Our calculation = a figure this article derived, with the assumptions spelled out
Not yet confirmed = still in development or planned, with nothing yet settled or delivered
General explanations of the physics and materials-design interpretations are marked separately as Commentary.

1. What SerDes and optical interconnects are (the short version)

  • SerDes: a transmit-and-receive circuit that turns the wide parallel data inside a chip into a few high-speed serial signals for sending (serialisation), and turns received serial signals back into parallel data (deserialisation). The faster it runs, the more the wiring distorts the waveform, so it also includes circuits to correct for that (commentary)
  • Optical interconnect: replacing some of the signals between chips or between pieces of equipment with light. Beyond the distance at which electrical loss becomes too large, light takes over (commentary)
  • Where the boundary lies: the IEEE P802.3dj objectives for 200 Gb/s per lane include at least 1.0 m over copper twinaxial cable and, optically, at least 500 m and 2 km over single-mode fibre, among othersSourced. The division of labour — copper within a few metres, light beyond — is written straight into the standard's objectives (our commentary)
How this fits with the rest of the series

Bringing optics closer to shorten the electrical stretch was covered in our Co-packaged Optics explainer and our explainer on NPO and LPO, and optical modules that plug into the front panel in our explainer on optical transceivers. This article deals with the premise behind those discussions: why electrical wiring reaches only so far, and how far that is. Signalling formats such as PAM4 are covered in our explainer on optical modulation and modulation formats.

2. What a SerDes does — parallel to serial, then making sense of a damaged waveform

What a SerDes does (schematic) Serialise on the transmit side; on the receive side, read the waveform the wiring has distorted and restore parallel data Parallel data Transmit serialise Tx equalisation Receive equalise, decide back to parallel Parallel data Wiring (package, board, connector, cable) High frequencies fade and edges slow down Waveform sent Waveform received The greater the wiring loss, the bigger and more power-hungry the SerDes compensation Note: schematic only. Compensation (Tx emphasis, Rx equalisation, A/D and digital processing) varies by implementation. Note: the LPO MSA specification treats the host as a "DSP based SerDes" and relies on its compensation for the linear optical link. Note: the sentence in the bottom band is our general framing.
Fig. 1 Conceptual diagram (vector drawing). A schematic of the general workings of a SerDes. That the host side is a DSP-based SerDes follows the LPO MSA specification [Ref. 5]. The division into circuit blocks and the waveform shapes are schematic and do not represent any particular circuit.

Running a few wires at high speed saves chip pins and wiring area compared with laying out dozens of parallel wires. The price is that high-speed signals fade in the wiring and smear into the symbols before and after them. A SerDes boosts the high frequencies as it transmits, equalises the distorted waveform as it receives, and decides each symbol afresh (commentary). NVIDIA says advances in GPU-to-GPU communication have been driven by innovation in "high-speed low-power SerDes"Sourced.

3. Why copper loses out at high frequencies

Signals in electrical wiring weaken for two main reasons (commentary).

  • Conductor loss: as frequency rises, current flows only near the surface of the conductor (the skin effect). The effective cross-section shrinks, so resistance rises, and roughness on the copper surface makes the current's path longer still
  • Dielectric loss: the molecules of the insulator that supports the wiring (board resin or cable insulation) cannot keep up with a high-frequency electric field and lose energy as heat. The loss grows in proportion to the material's dissipation factor (Df, tanδ) and to frequency

Both grow with frequency, so the same wiring loses more the faster it is driven, and the only way to stay within the same loss is to make the wiring shorter (commentary). That is why standards define loss in the form "so many dB at so many GHz".

4. Our calculation: loss budgets lined up as "amplitude left"

Standards and implementation agreements set a ceiling on allowable loss for each application. For the generation at about 100 Gb/s per lane (Nyquist frequency about 26.56 GHz), they line up as follows.

ApplicationLoss ceiling (as stated in the document)FrequencySource
Chip to chip, or chip to optical engine (XSR+)Up to 13 dB bump to bumpNyquist frequencyOIF CEI-112G-XSR+-PAM4
LPO host-to-module electrical channel16 dB (extended from 13 dB in the linear specification)26.56 GHzLPO MSA 100G-DR-LPO
LPO ASIC die to module dieAssumed to be 20 dB or less—LPO MSA 100G-DR-LPO
Backplane (100 Gb/s per lane)28 dB or less26.56 GHzIEEE 802.3ck and 802.3df objectives
Backplane (200 Gb/s per lane)40 dB or less, die to die53.125 GHzIEEE P802.3dj objectives

All Sourced (OIF announcement [Ref. 4], LPO MSA specification [Ref. 5], IEEE 802.3ck objectives [Ref. 1], 802.3df objectives [Ref. 2], P802.3dj objectives [Ref. 3]). "—" marks a cell where this article did not confirm a stated frequency.

Loss ceilings as the fraction of amplitude that arrives (our calculation) Amplitude left = 10^(-dB/20). Bar length is proportional to amplitude left (100% = 400 px) 13 dB XSR+ (chip to optical engine) 16 dB LPO electrical channel 20 dB LPO die to die 28 dB Backplane 100G 40 dB Backplane 200G about 22% about 16% 10% about 4% 1% Note: 13, 16, 20, 28 and 40 dB come from OIF, LPO MSA and IEEE 802.3ck/802.3df/P802.3dj documents; frequencies differ by use. Note: conversion to amplitude is our calculation. In power (amplitude squared), 28 dB is about 0.16% and 40 dB is 0.01%. Note: each standard measures loss over a different span (from where to where), so this is not a strict like-for-like comparison. Note: 40 dB is at 53.125 GHz; the others are at about 26.56 GHz (Nyquist).
Fig. 2 Drawing that includes our calculation (vector drawing). The loss ceilings are values from documents by OIF [Ref. 4], the LPO MSA [Ref. 5] and IEEE [Refs. 1, 2 and 3]. The amplitude and power fractions are this article's conversions, not published values. Because each document measures loss over a different span, this is not a strict comparison.

For a 200 Gb/s backplane, the objective is to work when only 1% of the launched amplitude arrivesOur calculation. From that 1% of a signal, the SerDes has to decide which of the four PAM4 levels was sent (our commentary).

5. Our calculation: what happened when the lane rate doubled

From 100 to 200 Gb/s per lane: how the IEEE objectives changed Frequency for measuring loss Backplane loss ceiling Copper cable reach objective 26.56 GHz ↓ 53.125 GHz doubled 28 dB ↓ 40 dB amplitude left: about 4% to 1% 2 m ↓ 1.0 m halved Even with 12 dB more loss allowed, the copper cable reach objective was halved Note: 100 Gb/s values from the 802.3ck (adopted March 2018) and 802.3df objectives; 200 Gb/s from the P802.3dj objectives (March 2024). Note: "doubled", "halved", "about 4% to 1%" and "12 dB" are our calculations. Reach objectives are "at least" values, not product reach.
Fig. 3 Drawing that includes our calculation (vector drawing). Frequencies, loss ceilings and reach objectives are values from the objectives documents for IEEE 802.3ck [Ref. 1], 802.3df [Ref. 2] and P802.3dj [Ref. 3]. The ratios, differences and fractions are this article's calculations, not published values.
Our calculation: how to read the numbers
  • Frequency: 53.125 / 26.56 = 2.0 times. Double the lane rate and the frequency at which loss is evaluated doubles tooOur calculation
  • Loss budget: 40 − 28 = 12 dB more. In amplitude terms, the allowable remainder goes from about 4.0% (28 dB) to 1.0% (40 dB), a quarter of what it wasOur calculation
  • Copper cable: the reach objective goes from "at least 2 m" to "at least 1.0 m", halfOur calculation

Assumptions and limits: the standard's objectives define what must work "at least at this distance and this loss"; they are neither an upper limit on reach nor measurements of products.

Even with SerDes evolving to read a signal four times weaker, copper cable length was halved — that is the heart of why light is being called for (our commentary). If lane rates double again, the same relationship may well repeat.

6. Scale-up networks — NVLink wires the rack in copper

AI computers have two kinds of network connecting GPUs: a scale-up network that ties GPUs within roughly a rack together so tightly that they behave like one big computer, and a scale-out network that joins many of those across the whole data centre (commentary). NVIDIA's NVLink is the leading example of the former, and the company describes it as a "scale-up networking fabric"Sourced.

NVLink generationBandwidth per GPUMaximum links per GPUGPU domainTotal bandwidthSupported platform
Fourth generation900 GB/s1887.2 TB/sHopper
Fifth generation1,800 GB/s188 / 72130 TB/s (NVL72)Blackwell
Sixth generation3,000 GB/s368 / 72216 TB/s (NVL72)Vera Rubin

All Sourced (specification table on NVIDIA's NVLink product page [Ref. 6]). The page labels the figures "Preliminary specifications; may be subject to change".

NVIDIA's technical blog describes the GB200 NVL72 configuration as followsSourced.

  • 18 compute nodes are interconnected by nine NVLink switch trays and cable cartridges
  • Each switch tray has 144 NVLink ports of 100 GB, so the nine trays connect all 18 NVLink ports on each of the 72 GPUs
  • The GPUs are densely interconnected with "a copper cable cartridge", and liquid cooling is used
GB200 NVL72: counting the NVLinks inside the rack (our calculation) … … 18 compute nodes 9 NVLink switch trays copper cables GPU side: 72 x 18 ports = 1,296 Switch side: 9 x 144 ports = 1,296 The counts match: every port pairs one-to-one Per GPU: 18 x 100 GB/s = 1.8 TB/s Whole rack: 72 x 1.8 TB/s ≈ 130 TB/s Per GPU, in bits 14.4 Tb/s (both directions combined; 7.2 Tb/s each way) carried over 1,296 copper NVLink links Note: 18 nodes, 9 trays, 144 ports, 18 ports/GPU, copper cables, 1.8 TB/s and 130 TB/s are from NVIDIA's blog and product page. Note: the multiplications, the consistency check and the conversion to bits (1 B = 8 bit) are our calculations. Note: the wiring diagram on the left is schematic and does not show real cable counts, routing or tray layout. Note: lanes and speed per NVLink port are not covered, as the NVIDIA material checked here does not state them.
Fig. 4 Drawing that includes our calculation (vector drawing). The configuration and bandwidth figures follow NVIDIA's technical blog [Ref. 7] and NVLink product page [Ref. 6]. The port-count multiplication, the bandwidth multiplication and the conversion to bits are this article's calculations. The wiring diagram is schematic and does not show the real structure.

What stands out is that NVIDIA chose to carry bandwidth of 14.4 Tb/s per GPU in both directions combined (7.2 Tb/s each way, equivalent to 4.5 optical modules at 1.6 Tb/s; our calculation) over copper inside the rack. As Section 5 showed, copper is still the simplest medium over short distances. Packing 72 GPUs into a single rack and cooling them with liquid can also be read, turned the other way round, as a way of fitting everything within the distance copper can reach (our commentary).

7. A materials engineer's view (1): the loss budget is spent on resin and copper foil

Cross-section of board wiring (schematic): where loss arises Ground plane (copper) Ground plane (copper) Insulating resin (dielectric) Surface roughness of the copper foil Differential signal traces (a pair) Conductor loss HF current crowds to the surface so copper roughness matters rises with frequency Dielectric loss resin molecules lag the field so the dissipation factor (Df) matters rises almost in proportion to frequency Note: schematic based on general transmission-line physics (commentary). Layer thickness, trace width and roughness are exaggerated. Note: real layer stacks, the presence of glass cloth and resin types vary by product. Note: the LPO MSA specification asks that ASIC package, host board and module board losses each stay within recommended ranges. Note: no numerical breakdown of loss is shown, as the primary sources checked here do not give one.
Fig. 5 Conceptual diagram (vector drawing). This article's schematic based on general transmission-line physics. Keeping each segment's loss within recommended ranges follows the LPO MSA specification [Ref. 5]. The layer stack, dimensions and roughness are exaggerated for illustration and do not show the cross-section of any particular board.
Why this matters for materials engineers: "28 dB" and "40 dB" are budgets handed out to materials

What the standards define is the total loss from the die of the transmitting chip to the die of the receiving chip, or from terminal to terminalSourced. The chip's package substrate, the printed-board wiring, connectors and cables — all of them share that one budget. The LPO MSA specification's figure showing recommended loss ranges for the ASIC package, the host board and the module board is one example of how it can be divided upSourced.

Once the wiring length is fixed, materials are the only lever left for lowering loss (our commentary).

  • Low-dissipation-factor resins: lower dielectric loss. But low-Df resins generally involve trade-offs with adhesion to copper, heat resistance and processability
  • Smooth-surfaced copper foil: lowers conductor loss. But the roughness of copper foil was there in the first place for adhesion to the resin (the anchor effect). The smoother it gets, the more adhesion has to be secured by other means
  • Cable dielectrics: the same applies to copper cable. The loss of the insulating material around the conductor sets the reach

Each time the lane rate doubles, the same length of wiring loses more. Even with the standard widening the loss ceiling from 28 dB to 40 dB, the increase cannot be absorbed by SerDes progress alone, and lower-loss materials get built in as a premise, generation after generation — that is the structure behind the demand for new high-speed board materials with every generation (our commentary).

8. A materials engineer's view (2): how far copper reaches is a boundary set by materials

Why this matters for materials engineers: the copper/optics boundary is not fixed, it moves with how good the materials are

Under the IEEE objectives, copper cable at 200 Gb/s per lane must reach "at least 1.0 m"Sourced. NVIDIA, meanwhile, links the inside of the GB200 NVL72 rack with copper cable cartridgesSourced, and pairs it with InfiniBand and Ethernet optical networks for scale-out (the GB300 NVL72 product page lists pairing with Quantum-X800 InfiniBand, Spectrum-X Ethernet and ConnectX-8 SuperNIC)Sourced.

So the boundary today sits close to "copper inside the rack, light outside it" (our commentary). Where exactly it falls is decided by a three-way tug of war.

  • The copper side: the material losses of cables, boards and connectors, and the compensating power of the SerDes
  • The optical side: the power and cost of optical modules (optical engines), and their reliability (see our explainers on optical transceivers and on Co-packaged Optics)
  • The packaging side: how densely things can be packed and still be cooled (NVL72 uses liquid cooling)

If low-loss resins and smooth copper foil advance by a generation, copper reaches a little further and the switch to light is pushed back. Conversely, if the power and cost of optical engines fall, the boundary moves into the rack. Optical communication materials and high-speed board materials are pushing on the same boundary from opposite sides — which also means a materials supplier may have a stake in both (our commentary).

9. What is still hard

(1) The standard for 200 Gb/s per lane is still being written

Final approval of IEEE P802.3dj could not be confirmed from primary sources as of this article's research (see our explainer on optical transceivers)Not yet confirmed. Looking further ahead to around 400 Gb/s per lane, a P802.3dj task force document lists the start of work on 400 Gb/s signalling (a Call for Interest, CFI) as a planned itemSourced. How many metres copper will reach at that point, or whether it will reach at all, had not been settled as of this article's researchNot yet confirmed.

(2) How far scale-up networks will stretch

NVIDIA's technical blog says fifth-generation NVLink can connect up to 576 GPUs in a single NVLink domainSourced. What would link the segments when a scale-up network is extended beyond one rack is not described specifically in the NVIDIA material this article checked. The timing and method of taking scale-up networks optical could not be confirmed as of this article's researchNot yet confirmed.

(3) What this article does not cover

SerDes power consumption (pJ/bit), loss by board material (dB per inch), and the number and speed of electrical lanes per NVLink port are not given, because they did not appear in the primary sources this article could open and check, or were not available in a comparable form.

The article in summary
  • A SerDes is a transmit-and-receive circuit that turns parallel data into serial for sending and makes sense of the distorted waveform on arrival (commentary)
  • Copper loss arises in the conductor (skin effect, surface roughness) and in the dielectric (dissipation factor), and grows with frequency (commentary)
  • Going from 100 to 200 Gb/s per lane, the evaluation frequency doubled, the loss budget went from 28 to 40 dB, and the copper cable reach objective from 2 m to 1.0 mSourced
  • 40 dB means only 1% of the launched amplitude arrivesOur calculation
  • GB200 NVL72 links 72 GPUs with copper cable cartridges, carrying 1.8 TB/s (14.4 Tb/s) per GPUSourced (conversion to bits: Our calculation)
  • The copper/optics boundary moves with the tug of war between low-loss resins and smooth copper foil on one side, and the power and cost of optical engines on the other (our commentary)

10. Glossary

SerDes
Serialiser/deserialiser. A circuit that converts parallel data into high-speed serial signals for transmission and reception.
Lane
A single signal stream carried on one differential pair.
Nyquist frequency
Half the baud rate. The reference frequency at which loss limits are specified.
Insertion loss
How much a signal weakens on its way through the wiring (dB). At 20 dB, amplitude falls to a tenth.
Equalisation
Restoring the high-frequency content lost in the wiring and bringing a distorted waveform back towards its original shape.
Skin effect
The tendency of high-frequency current to concentrate near the surface of a conductor.
Dissipation factor (Df)
How much of the electric field's energy an insulating material loses as heat. The smaller, the lower the loss.
Backplane
The board wiring that connects boards to one another inside a piece of equipment.
Twinaxial cable
A copper cable for high-speed differential signals in which a pair of conductors is wrapped in dielectric and shielding.
XSR
Extra Short Reach. The OIF class for very short electrical links between chips, or between a chip and an optical engine.
Scale-up network
A network that ties a handful to a few dozen GPUs together tightly enough to act as one computer. NVLink, for example.
Scale-out network
A network that connects many servers and racks. InfiniBand or Ethernet.
NVLink
NVIDIA's GPU-to-GPU interconnect. NVLink Switch interconnects every GPU in the rack.

11. References (primary sources)

  1. IEEE 802.3 "IEEE 802.3ck 100 Gb/s per Electrical Lane Objectives", March 2018 (PDF) — ieee802.org
  2. IEEE 802.3 "Adopted IEEE P802.3df Objectives", 17 November 2022 (PDF) — ieee802.org
  3. IEEE 802.3 "Adopted IEEE P802.3dj Objectives", 14 March 2024 (PDF) — ieee802.org
  4. OIF "OIF Unveils CEI-112G-XSR+-PAM4 Extended Extra Short Reach Implementation Agreement ...", January 2024 — oiforum.com
  5. LPO MSA "100G-DR-LPO Revision 1.0", March 2025 (PDF) — lpo-msa.org
  6. NVIDIA "NVLink & NVLink Switch", product page (specification table) — nvidia.com
  7. NVIDIA "NVIDIA GB200 NVL72 Delivers Trillion-Parameter LLM Training and Real-Time Inference", technical blog — developer.nvidia.com
  8. NVIDIA "GB300 NVL72", product page — nvidia.com
  9. IEEE P802.3dj Task Force "Timeline Consideration", 9 December 2025 (PDF) — ieee802.org

12. Claim-to-source audit

Claim in the textBasisLabel
The objectives, for 100 Gb/s per lane, of an electrical backplane with insertion loss of 28 dB or less (26.56 GHz) and at least 2 m over copper twinaxial cable (adopted March 2018)IEEE 802.3ck objectivesReference 1 https://www.ieee802.org/3/ck/P802_3ck_Objectives_2018mar.pdfSourced
The objectives, for 800 Gb/s (eight lanes), of an electrical backplane at 28 dB or less (26.56 GHz) and at least 2 m over copper twinaxial cableIEEE P802.3df objectivesReference 2 https://www.ieee802.org/3/df/proj_doc/objectives_P802d3df_221117.pdfSourced
The objectives, for 200 Gb/s per lane, of die-to-die insertion loss of 40 dB or less (53.125 GHz), at least 1.0 m over copper twinaxial cable, and at least 500 m and 2 km over SMF, among othersIEEE P802.3dj objectivesReference 3 https://www.ieee802.org/3/dj/projdoc/objectives_P802d3dj_240314.pdfSourced
That CEI-112G-XSR+-PAM4 is a 112 Gb/s PAM4 electrical interface between dies and between a die and an optical engine, specifying bump-to-bump insertion loss up to 13 dB at the Nyquist frequency and 36 to 58 Gsym/s, targeting MCM, CPO and NPOOIF announcement (January 2024)Reference 4 https://www.oiforum.com/oif-unveils-cei-112g-xsr-pam4-extended-extra-short-reach-implementation-agreement-paving-the-way-for-advanced-interconnectivity/Sourced
That the LPO electrical channel loss ceiling is extended from 13 dB to 16 dB (26.56 GHz), that 20 dB or less is assumed from ASIC die to module die, and that recommended loss ranges are shown for each segment. That the host is a DSP-based SerDesLPO MSA 100G-DR-LPO specificationReference 5 https://www.lpo-msa.org/files/live/sites/lpomsa/files/specs/LPO_MSA_Specification_v1p0_final.pdfSourced
That NVLink is a "scale-up networking fabric". Bandwidth per GPU by generation (900 / 1,800 / 3,000 GB/s), maximum links (18 / 18 / 36), GPU domain, total bandwidth (7.2 TB/s / 130 TB/s / 216 TB/s) and supported platforms. That the specifications are preliminary and may changeNVIDIA NVLink product pageReference 6 https://www.nvidia.com/en-us/data-center/nvlink/Sourced
That GB200 NVL72 interconnects 18 compute nodes with nine NVLink switch trays and cable cartridges. That each switch tray has 144 NVLink ports of 100 GB, connecting the 18 ports on each of the 72 GPUs. That the GPUs are densely interconnected with "a copper cable cartridge" and liquid cooling is used. 1.8 TB/s (bidirectional) per GPU. That fifth-generation NVLink can connect up to 576 GPUs in one domain. That innovation in "high-speed low-power SerDes" has driven GPU-to-GPU communicationNVIDIA technical blogReference 7 https://developer.nvidia.com/blog/nvidia-gb200-nvl72-delivers-trillion-parameter-llm-training-and-real-time-inference/Sourced
That GB300 NVL72 is paired with Quantum-X800 InfiniBand, Spectrum-X Ethernet and ConnectX-8 SuperNICNVIDIA GB300 NVL72 product pageReference 8 https://www.nvidia.com/en-us/data-center/gb300-nvl72/Sourced
That a P802.3dj task force document lists a CFI on 400 Gb/s signalling as a planned itemIEEE P802.3dj task force documentReference 9 https://www.ieee802.org/3/dj/public/25_1209/dambrosia_3dj_01b_251209.pdfSourced
Amplitude ratios (about 22%, about 16%, 10%, about 4% and 1%) and power ratios for 13, 16, 20, 28 and 40 dB. 53.125 / 26.56 = 2.0, 40 − 28 = 12 dB, the allowable remaining amplitude falling to a quarter, and the reach objective halving. 72 × 18 = 1,296, 9 × 144 = 1,296, 18 × 100 GB/s = 1.8 TB/s, 72 × 1.8 = 130 TB/s, 1.8 TB/s = 14.4 Tb/s (7.2 Tb/s each way), and 7.2 / 1.6 = 4.5, equivalent to 4.5 optical modules at 1.6 Tb/sOur calculation. The standards measure loss over different spans, so the comparison is not strict. 1 B = 8 bit is assumedOur calculation
Final approval of P802.3dj, copper reach at around 400 Gb/s per lane, and the timing and method of taking scale-up networks opticalStill in development or under study; an outlook not settled as of this article's researchNot yet confirmed
Explanations of how a SerDes works, of conductor loss (skin effect, surface roughness) and dielectric loss (dissipation factor), and of the distinction between scale-up and scale-out networks. The framing of the standards' loss budgets as budgets handed out to materials, the trade-offs of low-Df resins and smooth copper foil, the reading that the boundary sits close to "copper inside the rack, light outside", and the framing that the copper/optics boundary moves with a tug of war between materials and optical engines. The interpretation of NVL72's density and liquid cooling as a way of staying within copper's reachGeneral explanations of the physics, and this article's framing and commentary based on public material. Not views expressed by any of the companies or bodiesCommentary
SerDes power consumption, loss values by board material, and the number and speed of electrical lanes per NVLink portNot stated in this article, because they did not appear in the primary sources it confirmed, or were not available in a comparable formCommentary
That Figs. 1 and 5 are explanatory drawings, that Figs. 2, 3 and 4 are drawings that include our calculation, and that the hero image is AI-generatedA note by this articleCommentary

Last updated 26 September 2026. Sources are limited to primary material (IEEE 802.3 objectives documents and task force material, OIF announcements, the LPO MSA specification, and NVIDIA's official product pages and technical blog). Because the article includes general explanations of the physics and materials-design interpretations, those are marked as Commentary and kept separate from sourced fact. SerDes power consumption, loss values by board material and the lane make-up of NVLink are not given, because they could not be confirmed in published primary sources. NVIDIA's specification table gives values the company describes as preliminary. All figures are for explanation. Figs. 1 and 5 are vector drawings, Figs. 2, 3 and 4 are vector drawings that include our calculation, and the hero image is AI-generated; none of them shows the structure, wiring or dimensions of a real product.

🌐 Japanese