1. What CoWoS is — the name is the process

CoWoS stands for Chip on Wafer on Substrate. It looks like jargon, but the name is simply the assembly sequence written out in order.

• Chip on Wafer: the chips — logic dies and HBM stacks — go onto a wafer first. That wafer is the interposer.
• on Substrate: the piece is then cut out of that wafer and mounted on the package substrate.

TSMC describes CoWoS as a 2.5D advanced packaging technology that integrates multiple SoCs and high bandwidth memory (HBM) stacks to deliver high computing performance and memory bandwidth in a productSourced (TSMC).

Fig. 1 · How CoWoS is assembled

2. Why it is needed

Several threads from earlier articles in this series come together here.

TSMC states that the CoWoS platform has kept evolving since volume production began in 2012, and that the arrival of generative AI in the second half of 2022 pushed market demand higher stillSourced.

3. Three variants: CoWoS-S, -R and -L

CoWoS comes in three variants, and what separates them is what the chips are connected through.

Fig. 2 · Cross-section comparison of the three CoWoS variants

All of the above is Sourced (TSMC CoWoS technology page). TSMC recommends CoWoS-L or CoWoS-R for sizes beyond 3.3 reticles.

4. How the reticle limit was beaten — mask stitching

This, to my mind, is the most interesting part of the whole technology.

As the article on chiplets explained, there is an upper bound on the area a lithography scanner can print in a single exposure: the reticle limit. TSMC puts one reticle at roughly 830 mm²Sourced.

Yet an interposer has to carry a logic die and several HBM stacks side by side. There is no way that fits inside 830 mm².

The answer: stitch the exposures together

On 3 March 2020, TSMC announced, in collaboration with Broadcom, the industry's first and largest 2x reticle size interposer, about 1,700 mm² in areaSourced.

What made it possible was TSMC's unique mask stitching process that allows the interposer to extend beyond full reticle sizeSourced (TSMC, 3 March 2020).

Fig. 4 · The idea behind mask stitching

The configuration that resulted was published too: multiple logic SoC dies together with up to six HBM cubes, up to 96 GB in total, and up to 2.7 TB/s of bandwidth. That is 2.7 times the CoWoS offering of 2016Sourced.

Who did what was stated as well: Broadcom defined the complex configuration of the top dies, interposer and HBM, while TSMC developed the robust manufacturing process that maximises yield and performanceSourced.

5. How big does it get (the roadmap)

TSMC has published its plans for scaling CoWoS up, one technology symposium at a time.

The reticle counts and dates are Sourced (published by TSMC). The areas and percentages are Our calculation, taking one reticle as 830 mm² and a 300 mm wafer as π × 150² = approx. 70,686 mm². TSMC publishes the areas for the 2-reticle and 3.3-reticle cases directly.

Fourteen reticles works out to roughly a 108 mm square of siliconOur calculation. A single product would then occupy about one sixth of a whole 300 mm wafer.

6. A materials engineer's view: large-area silicon is an awkward object

Looked at from the materials side, CoWoS is the art of handling a piece of silicon that has no business being that large, without breaking it.

(1) A huge piece of silicon, thinned and bonded

A 3.3-reticle interposer is about 2,700 mm², which is a 52 mm square of siliconOur calculation. On top of that, the interposer has to be thinned so that TSVs can run right through it. Large, thin, stiff and brittle — every condition for warpage and cracking is present at once.

(2) The CTE mismatch scales with the dimension

(3) Accuracy at the seam

Mask stitching requires the wiring to join up across the boundary between adjacent exposure fields. The overlay accuracy achieved there translates directly into wiring yield. The larger the interposer, the more seams there are; and because the area is large, temperature drift during exposure and wafer warpage show up as misregistration all the more readily.

(4) Building function into the interposer

For CoWoS-S and CoWoS-L, TSMC lists an eDTC, an embedded deep trench capacitorSourced. Deep trenches are etched into the silicon, then lined with a dielectric and electrodes to form a capacitor.

So the interposer is not merely a wiring board; it is somewhere you can build the parts that damp power-supply noise. Depositing a uniform film all the way down a deep trench is a demanding piece of process technology, and its presence here shows how far front-end materials and process technology have moved into packaging.

7. Where it sits among TSMC's "three pillars"

TSMC organises its chip-to-chip interconnect technologies into three pillarsSourced (TSMC Research).

TSMC lists the strengths of the silicon interposer as high wiring density, high capacitance per unit area, and a large reticle size for exascale HPC and AISourced. The fact that "large reticle size" is listed as a strength alongside the performance metrics tells you a great deal about the character of this technology.

8. What is still hard

(1) Capacity

CoWoS needs an interposer built on a silicon process line, just like front-end manufacturing, plus dedicated assembly equipment. Adding equipment takes time, so capacity cannot follow a demand spike quickly. TSMC itself says demand grew further with the arrival of generative AISourced.

(2) Size versus yield

The more area a part occupies, the higher the chance it contains a defect. And by that point the interposer is already carrying expensive dies that have been tested and confirmed good. A failure at the final assembly stage throws away everything invested up to that point.

(3) Heat

Ten logic dies and twenty HBM stacks in a single package: if the 2028 plan is realised, getting the resulting heat out becomes the next wall. TSMC's research publications include work on liquid cooling for HPCSourced.

9. Glossary

10. Primary sources

1. TSMC "CoWoS®" technology page — 3dfabric.tsmc.com
2. TSMC "TSMC and Broadcom Enhance the CoWoS Platform with World's First 2X Reticle Size Interposer", 3 March 2020 — pr.tsmc.com
3. TSMC "TSMC Unveils Next-Generation A14 Process at North America Technology Symposium", 23 April 2025 — pr.tsmc.com
4. TSMC "TSMC Debuts A13 Technology at 2026 North America Technology Symposium", April 2026 — pr.tsmc.com
5. TSMC Research "Interconnect / Off-chip Interconnect" — research.tsmc.com
6. TSMC "TSMC-SoIC®" technology page — 3dfabric.tsmc.com

11. Claim-to-source audit

Last updated 20 September 2026. Sources are limited to TSMC's official announcements and technology pages. All figures are explanatory concept graphics. Visual-overview figures are shown as AI-generated conceptual images, matching the Japanese edition. Vector drawings are retained where they carry quantitative values or precision-critical technical labels. AI-generated images do not depict real equipment, products, facilities, dimensions or exact cross-sections; replaced source SVG overview drawings remain in the HTML but are hidden.