1. What EMIB and EMIB-T are (the short version)

EMIB is a technology that buries a small silicon bridge in a cavity of the substrate and connects only the facing edges of neighboring chips with fine wiring. EMIB-T is the version in which TSVs have been added to that bridge.

• What EMIB is: Intel calls it "the industry's first 2.5D interconnect solution using bridges embedded in the substrate." The bridge sits in a substrate cavity held in place with adhesive, and dielectric and metal build-up layers are then added on top [Ref. 1] Sourced
• What EMIB-T is: Intel says that, because demand for high-bandwidth memory (HBM) raised the need for vertical power delivery with minimal DC and AC noise, Intel Foundry added TSVs to EMIB-T [Ref. 1]. An Intel conference paper describes a direct power-delivery path through the bridge, from the package bottom to the ASIC and the HBM [Ref. 18] Sourced
• Where it stands: EMIB has been in volume production since 2017 [Refs. 1, 2] Sourced. EMIB-T was announced as a new offering in April 2025 [Ref. 5], and a 2026 conference paper reports on the reliability of a "1st generation" during initial development [Ref. 18] Sourced. We could not find a primary source showing that EMIB-T has entered volume production. Not yet confirmed

2. What came first, and when — from the idea to today

Ravi Mahajan, the Intel engineer known as the developer of EMIB, described the history in an Intel interview published in May 2026. In the early 2000s the team asked whether packaging had its own scaling roadmap, concluded that interconnect density was a key limit, and explored putting silicon interconnect directly into the package. In his words, "By 2013, we were confident enough to bring EMIB into a production program and then introduced it to the public the following year" [Ref. 6] Sourced. He adds that the idea was simple but "required solving complex challenges in materials, stress management, and manufacturing" [Ref. 6] Sourced.

* The April 2025 item is an announcement of a new offering. An Intel newsroom article of July 2026 also says that "in 2026 the latest development is EMIB-T" [Ref. 7], but that sentence alone does not establish a date, so this article uses the 29 April 2025 announcement.

One question worth asking is which product was first. Intel's 2017 announcement does say "first consumer product" [Ref. 9], but we could not find a primary source that settles which product, counting data-center parts and FPGAs, came first. Altera's 2015 announcement was a forward-looking statement about Stratix 10 [Ref. 10], and the actual shipment date is not confirmed in the sources we reviewed.

3. Structure — buried in the substrate, wired out from above

In EMIB the silicon bridge sits in a cavity of an organic substrate, build-up layers are formed over it, and vias connect to fine pads on the bridge. The two neighboring chips sit on fine bumps directly above the bridge, near their facing edges (for how this differs from a full-sheet interposer, see our explainer on bridges). Here we gather what the primary sources reveal about materials and how it is made.

• Bridge substrate material: an Intel patent filed in 2012 (granted in 2014) says the bridge substrate may be glass or a semiconductor such as high-resistivity silicon, with electrical routing formed on it. The bridge is placed in a cavity formed in the package substrate, and an example is given in which a die-attach adhesive couples the bridge substrate to the epoxy material of the package substrate [Ref. 19] Sourced
• How fine the wiring is: the background section of another Intel patent says EMIB uses a silicon piece carrying ultrafine line-and-space structures (for example 2 µm / 2 µm), which can be fabricated with silicon back-end-of-line technology but are beyond the capability of organic substrate manufacturing. One or more such pieces are embedded in a cavity skived into a standard organic substrate and bridge the fine bump-pitch areas between dies (55 µm pitch is given as an example) [Ref. 21] Sourced
• No TSVs (in conventional EMIB): the 2016 paper lists among EMIB's advantages that it provides high-density interconnect cost-effectively without TSVs, and that it can support many large die over an area much greater than the reticle limit [Ref. 13]. The 2019 paper puts the interconnect density at 500-1000 I/O/mm and says the link is realized while leaving the rest of the package structures and designs unaffected [Ref. 14] Sourced

4. EMIB-T — why put TSVs through the bridge

Conventional EMIB bridges had no TSVs. The background section of an Intel patent filed in 2013 says: "unlike silicon interposers, the embedded interconnect bridge die does not have through-silicon vias to enable power connections from outside the package to the bridge. This is in part because of the very thin structure of such a bridge" [Ref. 20] Sourced. With no vertical path beneath the bridge, power has to reach the chips by passing around it (our commentary, consistent with Intel's own wording "instead of around it" [Ref. 7]).

EMIB-T adds the TSVs. Intel says it did so because demand for HBM has increased "the need for vertical power delivery with minimal DC and AC noise" [Ref. 1] Sourced. An Intel newsroom article of July 2026 describes EMIB-T as adding "channels through that bridge to deliver power directly to the chips, instead of around it" [Ref. 7] Sourced.

* On design conversion, Intel says only that EMIB-T "can ease the enablement of IP integration from other packaging designs" and does not explain how [Ref. 2].

Published EMIB-T numbers, and the conditions behind them

* Bridge dimensions and thickness, TSV diameter, pitch and count, the start of volume production, and the names of products using EMIB-T could not be confirmed from the primary sources we reviewed. Some news reports give a package size of "120 mm × 180 mm", but we could not confirm it in primary sources and do not use it.

5. Embedding the bridge: process steps and materials issues

Intel states that the EMIB assembly flow is a standard semiconductor package-assembly flow, "with the only difference being the manufacturing of the substrate" [Ref. 1] Sourced. So the materials and process issues concentrate on the part where a piece of silicon is buried in the substrate. Below we split that part into five steps using Intel's technical document plus the background and embodiments of Intel's published patents. A patent says "this is the problem, and this is a way it could be solved"; it does not describe the current production process.

(1) Forming the cavity: laser or lithography

The background of an Intel patent (filed 2018, granted 2022) describes the limits of today's cavity formation as follows [Ref. 21] Sourced.

• The cavity is made by laser-skiving a standard organic substrate.
• Bump pitch is projected to go to 30 µm or lower, while bump thickness variation must stay below 10 µm for assembly.
• But "multi-layer organic substrates can have thickness variation of over 40 µm even before reaching the final layer." The layer thickness the laser has to skive is not uniform and varies within a lot and even within a panel, so there is a higher chance of laser punch-through that damages the underlying copper pads.
• Cavity dimensional and location tolerances must improve when smaller silicon bridges are used.

The same patent adds that the trepanning method, in which laser shots are overlapped, produces misalignment between shots as the galvanometer moves, gives a wave-like perimeter, and that locations with maximum spot overlap take a larger thermal hit and are more prone to copper-pad delamination [Ref. 21] Sourced. As an alternative, it presents embodiments in which the cavity is defined lithographically.

All Sourced (background and embodiments of Intel patent US 11,322,444 B2 [Ref. 21]). We could not confirm whether this approach is used in any product.

(2) Placing and fixing the bridge

The patent shows an embodiment in which the bridge is fixed to the floor of the cavity with an adhesive such as a die bond film (DBF) [Ref. 21]. A patent filed in 2012 likewise shows the bridge substrate bonded to the epoxy material of the package substrate with a die-attach adhesive or similar [Ref. 19] Sourced. The embodiments also give the following numbers [Ref. 21] Sourced.

• Example cavity width: about 10 mm (any size is allowed as long as it holds the bridge)
• Gap G between the bridge sidewall and the cavity sidewall: embodiments of 100 µm or less, 50 µm or less, and 20 µm or less
• The bridge is thinner than the layer containing the cavity, so its top surface lies below the substrate surface in the first embodiments (coplanar and protruding cases are also described)
• Wiring on the bridge: line/space of 10/10 µm or less, and further 2/2 µm or less

(3) Wrapping in resin: gaps and voids

A build-up layer (the "third layer") is then formed over the bridge, fills the gap around it, and covers its sidewalls and top surface [Ref. 21] Sourced. Intel's technical document likewise says dielectric and metal build-up layers are added in this step [Ref. 1] Sourced. The patent itself notes that a cavity with a stepped overhang may be less reliable if the cavity cannot be fully filled [Ref. 21] Sourced.

From a materials standpoint this is the problem of filling a narrow gap, tens to a hundred micrometers wide, with build-up resin without voids (our commentary). Film flow and thickness uniformity are covered in our explainer on build-up film, and gap filling in our explainer on underfill.

(4) Bringing the wiring out, then mounting the chips

Fine pads on the bridge are connected through vias opened in the third layer [Ref. 21] Sourced. Because the bridge is buried and invisible, the accuracy with which the vias land on the pads of the bridge is tied to the positional tolerance of the cavity (our commentary). The bump pitch for the chips that go on top was reduced from 55 µm to 45 µm with 2nd-generation EMIB [Ref. 12] and has been reported scaled down to 25 µm for EMIB-T [Ref. 16] Sourced. For the joining and filling materials, see our explainers on bumps and underfill.

6. A materials engineer's view: the difficulty moved to the substrate side

The bridge approach avoids the difficulties of a full sheet of silicon (large area, TSVs, thinning) but takes on those of a joint between dissimilar materials inside the substrate. This section takes up three that can be examined with numbers.

(1) Expansion mismatch, expressed as a length

(2) How Intel approaches reliability testing

Intel's quality and reliability paper (June 2024) says advanced packages such as Foveros and EMIB require a more complex verification process [Ref. 12] Sourced. On temperature cycling it explains that "thermo-mechanically induced damage results from differences in the material properties of the constituent materials over the range of cycling temperatures," and lists solder-joint fatigue, package cracking, and interlayer-dielectric (ILD) cracking in the die and package as accelerated failure mechanisms [Ref. 12] Sourced. As example conditions it gives temperature cycling between 125 °C and −55 °C per JEDEC JESD22-A104, and an unbiased highly accelerated stress test (HAST) at 110 °C and 85% relative humidity per JESD22-A118. These are stated as examples and are not specification values for EMIB or EMIB-T [Ref. 12] Sourced.

(3) The variables researchers are looking at

Third-party finite-element work on EMIB reports the following. It is an analysis by Zhou and Wang of Fudan University with a 165 °C temperature rise applied [Ref. 22] Sourced.

• A bump diameter-to-pitch ratio of 0.3 optimizes the stress distribution
• A peripheral bump arrangement is better at reducing stress than other patterns
• The thinner the EMIB (bridge), the lower the maximum principal stress, linearly
• The number of EMIBs and the aspect ratio have minimal effect

These are results for a generalized model and not values for any specific product. One could read from them that thickening the bridge to accommodate TSVs might work against stress, but whether EMIB-T bridges are thicker than before is not confirmed (our commentary).

A different approach, which embeds the bridge in an organic redistribution layer (RDL), is discussed by ASE under the name fan-out embedded bridge. ASE says that small, thin silicon bridges and power components can exacerbate warpage during package assembly, that high warpage can lead to defects such as non-contact open, bridge, non-wet or stretch joints, and that controlling warpage is therefore crucial for OSATs [Ref. 27] Sourced. This is a structure different from EMIB; we cite it only because the same classes of defects are named as shared concerns of embedded-bridge approaches. Intel also lists, among its ECTC 2026 presentations, one on the creep behavior of assembly materials and its effect on package warpage, but we could not confirm the content [Ref. 8] Sourced.

7. How big can it get — multiples of the reticle

The metric EMIB-T puts forward is how many reticle fields of silicon one package can carry. Intel Foundry's blog (March 2026) explains that an interposer larger than one reticle has to be made by reticle stitching, which is complex and expensive, and that silicon bridges embedded in the substrate are a more cost-effective alternative [Ref. 3] Sourced. It then gives the following scale for EMIB-T.

• Today: die complexes of more than 6x the reticle size [Ref. 3] Sourced
• 2026: more than 8x (about 6,800 mm²) [Ref. 3] Not yet confirmed
• 2028: more than 12x (about 10,000 mm²), using 16 or more HBM4/HBM5 stacks and 30 or more EMIB-T bridges [Ref. 3] Not yet confirmed
• ECTC 2026 paper: more than 9x reticles of silicon on a package larger than 120 mm × 120 mm [Ref. 16] Sourced

* An Intel newsroom article of July 2026 says it is "scaling packages to 8x the industry standard today, and over 12x by 2028" [Ref. 7]. The March 2026 blog says more than 6x today and more than 8x this year [Ref. 3]. Because the dates and the baseline are worded differently, this article follows the breakdown in the March blog and treats 8x as a target for 2026.

Intel's account of how the manufacturing flow differs from an interposer

Intel Foundry's blog describes the difference in manufacturing flow as follows [Ref. 3] Sourced.

• In EMIB-T, small silicon bridges are fabricated on a wafer at very high density, giving about 90% wafer utilization. The bridges are then embedded in large-format organic rectangular panels, which are singulated.
• A full-size interposer, by contrast, has to be fabricated over the whole package footprint on a wafer, and for complexes of more than 8x the reticle this "can reduce wafer utilization to as low as 60%."
• Intel says the EMIB-T flow is well aligned with panel-based manufacturing.

This is Intel's account and does not rank EMIB against other approaches. Intel also says that bridge-based packaging from other foundries, which places local silicon interconnect (LSI) bridges in the interposer, needs more assembly steps [Ref. 3]; for the structural difference, see CoWoS-L in our CoWoS explainer. This article does not judge which is better.

8. Our calculation: HBM4 and HBM4E bandwidth

The EMIB-T paper states that operation above 12 Gb/s is feasible for HBM4E [Ref. 17] Sourced. The JEDEC HBM4 standard specifies a 2048-bit interface at up to 8 Gb/s, and up to 2 TB/s per stack [Ref. 24] Sourced. We combine the two.

In other words, the fast signals of one HBM stack cross a few millimeters of bridge edge. One can read the small size of the bridge as resting on numbers of this order (our commentary).

9. Foveros, EMIB 3.5D and Intel's other technologies

Intel's packaging technologies can be sorted into lateral (2.5D) and vertical (3D). EMIB connects chips sideways and Foveros stacks them. Using both gives EMIB 3.5D. Intel describes EMIB 3.5D as a hybrid that combines the vertically stacked chiplets of Foveros with the silicon-embedded bridge of EMIB in a single package, and says it addresses "the downsides of thermal warping, reticle size limits, and interconnect constraints" [Ref. 1] Sourced.

* The "2027" for Foveros-R is a "production ready" date and is a plan. The production timing of Foveros-B could not be confirmed. Intel describes Sapphire Rapids as a tiled SoC leveraging EMIB, and Ponte Vecchio as tiles joined through an EMIB tile and assembled with Foveros packaging [Ref. 11].

Intel's quality and reliability paper describes EMIB as providing high-bandwidth connectivity between multiple large chiplets without a silicon interposer, and says it can also connect multiple compute modules made with Foveros Direct 3D, a combination called EMIB 3.5D [Ref. 12] Sourced. It adds that this allows systems with a total silicon surface area far greater than was achievable with silicon interposers alone [Ref. 12] Sourced.

10. Availability to outside customers (Intel Foundry)

EMIB is a technology offered not only for Intel's own products but also to outside customers. What can be confirmed, however, is limited.

* Some news reports name customers, production timing and substrate suppliers. This article does not use them because they cannot be confirmed in official primary sources.

11. What we could not confirm

Here we list the points we could not confirm from primary sources after looking. We have not filled them in by guesswork.

12. Glossary

13. References

1. Intel "Embedded Multi-die Interconnect Bridge (EMIB) revolutionizes chip packaging interconnect technology," Technology Brief (July 2025, PDF) — intel.com
2. Intel Foundry "Advanced Packaging Innovations" — intel.com
3. Intel Foundry (Mark Gardner) "Intel Foundry's Advanced Packaging Innovations Lead the Industry in Scaling Past Reticle Limits," 3 March 2026 — community.intel.com
4. Intel Foundry (Mark Gardner) "Intel Foundry's Advanced Packaging Enables Next-Gen Technologies and Capacity," 29 September 2025 — community.intel.com
5. Intel "Intel Foundry Gathers Customers and Partners, Outlines Priorities," press release, 29 April 2025 — intc.com
6. Intel "Meet the Intel Pioneer Behind EMIB Chip Packaging" (interview with Ravi Mahajan), 28 May 2026 — intel.com
7. Intel "Intel's U.S. Advanced Packaging Enables Next-Generation AI Semiconductors," 29 July 2026 — intel.com
8. Intel Foundry (Lori Scott) "How Intel Foundry Packaging Technologies Redefine AI and HPC Scalability Limits at ECTC 2026," 2 June 2026 — community.intel.com
9. Intel "Intel Editorial: New Intel Core Processor Combines High-Performance CPU With Custom Discrete Graphics From AMD to Enable Sleeker, Thinner Devices," 6 November 2017 — intc.com
10. Altera News release on Stratix 10 FPGA and SoC architecture and heterogeneous 3D SiP integration (archive file name: altera-reveals-stratix-10-innovations…), 8 June 2015 (PDF) — download.intel.com
11. Intel "Intel Architecture Day 2021 Fact Sheet," 19 August 2021 (PDF) — download.intel.com
12. Intel "Quality & Reliability Vol. 6: Intel Advanced Packaging Technology Ensures High Quality & Reliability," Technical Paper (document dated June 2024, PDF) — cdrdv2-public.intel.com
13. R. Mahajan et al. (Intel) "Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect," 2016 IEEE 66th ECTC, pp. 557-565 (May 2016), DOI 10.1109/ECTC.2016.201 — doi.org
14. R. Mahajan et al. (Intel) "Embedded Multidie Interconnect Bridge—A Localized, High-Density Multichip Packaging Interconnect," IEEE Trans. Components, Packaging and Manufacturing Technology, vol. 9, no. 10, pp. 1952-1962 (October 2019), DOI 10.1109/TCPMT.2019.2942708 — doi.org
15. R. Mahajan et al. (Intel) "Scaling EMIB—A Comprehensive Architecture Portfolio for Localized Interconnects," IEEE Trans. Electron Devices, vol. 72, no. 7, pp. 3911-3914 (July 2025), DOI 10.1109/TED.2025.3574287 — doi.org
16. T. Ibrahim et al. (Intel) "Scaling the EMIB-T Advanced Packaging Technology to Address the Future HPC/AI Demand," 2026 IEEE 76th ECTC, pp. 277-282 (May 2026), DOI 10.1109/ECTC51846.2026.00051 — doi.org
17. Y. Mekonnen et al. (Intel) "Enabling 12+Gb/s HBM4E with EMIB-T Advanced Packaging Technology," 2026 IEEE 76th ECTC, pp. 455-460 (May 2026), DOI 10.1109/ECTC51846.2026.00078 — doi.org
18. E. Armagan et al. (Intel Foundry) "Quality & Reliability Characterization of EMIB-T (TSV) Advanced Packaging Technology," 2026 IEEE International Reliability Physics Symposium (March 2026), DOI 10.1109/IRPS61424.2026.11499343 — doi.org
19. Intel (patent) US 8,872,349 B2, "Bridge interconnect with air gap in package assembly" (filed 11 September 2012, granted 28 October 2014) — patents.google.com
20. Intel (patent) US 8,901,748 B2, "Direct external interconnect for embedded interconnect bridge package" (filed 14 March 2013, granted 2 December 2014) — patents.google.com
21. Intel (patent) US 11,322,444 B2, "Lithographic cavity formation to enable EMIB bump pitch scaling" (filed 23 March 2018, granted 3 May 2022) — patents.google.com
22. Y. Zhou and J. Wang (Fudan University) "Thermal Stress Analysis and Key Influencing Factors for the EMIB in Chiplet Packaging," Integrated Circuits and Systems, vol. 2, no. 1 (March-April 2025), DOI 10.23919/ICS.2025.3547674 — doi.org
23. Amkor Technology "Amkor-Intel Partnership Expands EMIB Packaging Capacity," 30 April 2025 — amkor.com
24. JEDEC "JEDEC and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC," 16 April 2025 — jedec.org
25. Sekisui Chemical Thermosetting interlayer insulation film (build-up film) product page (in Japanese) — sekisui.co.jp
26. Kyocera Fine ceramics for semiconductors, "Search by material properties" (in Japanese) — kyocera.co.jp
27. W. Wudjud et al. (ASE) "Warpage Evaluation in Embedded Bridge Package for Advanced Package Solutions," IMAPSource Proceedings (December 2025), DOI 10.4071/001c.151768 — doi.org

14. Claim-to-source audit

Last updated 2 October 2026. Sources are limited to primary material (Intel technical documents, blog posts, press releases and newsroom articles; an Altera release; abstracts of IEEE papers; Intel's published patents; and the official pages of Amkor and JEDEC). IEEE papers are behind a paywall, so this article relies on abstracts and Intel's explanatory posts and does not check numbers in the full text of the papers. Because the article includes structural readings and materials-design interpretations, those are marked as Commentary and kept separate from sourced fact. The start of EMIB-T volume production, adopting companies and products, bridge dimensions and TSV specifications, yield, substrate makers and capacity could not be confirmed from primary sources and are not stated here. Patent passages describe problems and embodiments and do not describe the current production process. All figures are explanatory concept graphics. Figs. 1, 3, 4, 5 and 6 are vector drawings; the hero image and Fig. 2 are AI-generated images, and none of them shows a real cross-section, micrograph or physical product.