Shanghai Jiao Tong University Develops FOWLP for Seamless Opto-Electronic Integration, Halving Signal Loss in Data Centers

August 30, 2026

IMAPS 3D InCites Content Platform China

Overview

Researchers at Shanghai Jiao Tong University have pioneered a fan-out wafer-level packaging (FOWLP) technique to integrate electronic and photonic components, significantly reducing signal loss and improving interconnect density in data centers. The approach leverages redistribution layers (RDL) for high-precision connections and benzocyclobutene as a low-dielectric insulating material, enhancing thermal stability and reducing transmission loss for high-frequency operations. This breakthrough is critical for overcoming current data transfer bottlenecks, promising substantial performance and efficiency gains for next-generation AI and HPC infrastructure.

In Depth

Key Findings

Researchers from Shanghai Jiao Tong University have made a significant leap in addressing the critical integration challenges of electronic and photonic components for high-speed data transfer in data centers. Their novel fan-out wafer-level packaging (FOWLP) technique achieves seamless integration, dramatically reducing signal loss and improving interconnect density in opto-electronic systems, paving the way for more powerful and energy-efficient computing.

Technical / Clinical Details

FOWLP for Hybrid Integration: The core innovation lies in the use of FOWLP to directly integrate dissimilar electronic and photonic chips. This method allows for a much tighter and more efficient connection compared to traditional packaging.
High-Precision Redistribution Layers (RDL): Essential for the FOWLP process, RDLs enable high-precision electrical and optical routing between the chips, facilitating complex interconnections with minimal signal degradation.
Benzocyclobutene (BCB) Dielectric: The selection of benzocyclobutene as a low-dielectric insulating material is crucial. BCB not only reduces high-frequency transmission loss but also significantly improves the thermal stability of the integrated package, which is vital for sustained high-performance operation in dense data center environments.
Addressing Bottlenecks: This advanced packaging solution directly tackles the bandwidth and power consumption bottlenecks inherent in traditional electrical interconnects, which become increasingly pronounced with the growing demands of AI and high-performance computing workloads.

Background & Context

The rapid expansion of AI and high-performance computing applications has placed immense pressure on data center infrastructure, particularly regarding the speed and efficiency of internal data transfer. While CPU and GPU computational power continues to advance, the electrical interconnects that link these processing units often become the limiting factor, hindering overall system performance. Silicon photonics and co-packaged optics (CPO) are recognized as key technologies to overcome these limitations by using light for data transmission. This research provides a crucial manufacturing pathway for the practical implementation of such integrated photonics, accelerating the transition from electrical to optical interconnects within compute units.

Strategic Significance & Outlook

This FOWLP technology represents a fundamental advancement for future data center architectures, AI supercomputers, and other high-performance computing clusters. By enabling ultra-dense and energy-efficient opto-electronic integration, it promises to significantly reduce the power consumption of data transfer while boosting overall computational throughput. The ability to seamlessly combine light and electronics on a single package will not unlock new levels of performance for AI training and inference, but also potentially accelerate the development of advanced applications in quantum computing and edge AI devices, broadening its impact across various industries globally.

Source: https://www.3dincites.com/2026/08/breaking-the-compute-barrier-with-light-silicon-photonics-co-packaged-optics-and-advanced-packaging/

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