Key Findings
According to the latest projections from Morgan Stanley, global demand for CoWoS (Chip-on-Wafer-on-Substrate) technology is set to experience an extraordinary 93% surge by 2027, reaching a total of 2.694 million units. This explosive growth is primarily fueled by the burgeoning AI and high-performance computing markets. Nvidia is expected to remain the dominant consumer, accounting for approximately 45% of this demand. A particularly significant development is the anticipated adoption of CoWoS packaging by AMD’s next-generation Venice CPU, with production entrusted to leading OSAT (Outsourced Semiconductor Assembly and Test) providers such as ASE/SPIL, Amkor, and Powertech Technology.
Technical / Clinical Details
CoWoS is an advanced packaging technology that integrates multiple logic dies and HBM (High-Bandwidth Memory) stacks onto a silicon interposer, which is then connected to an organic substrate. This technology dramatically enhances inter-chip data transfer speeds and improves power efficiency, making it indispensable for maximizing the performance of AI accelerators and HPC processors. AMD’s adoption of CoWoS for its Venice CPU marks a critical strategic shift, aimed at bolstering its competitiveness in the AI and data center markets. The Venice CPU is expected to be based on the Zen 5 architecture for the server market, and its CoWoS implementation will enable the efficient integration of large L3 caches, multiple CPU cores, and HBM stacks within a single package. This configuration will deliver exceptionally high processing power and memory bandwidth, previously unachievable with conventional packaging, significantly improving the efficiency of AI workloads.
Background & Context
The evolution of AI has introduced a new ‘bottleneck’ in semiconductor manufacturing: packaging. As chip miniaturization approaches its physical limits, performance gains are increasingly dependent on how efficiently and effectively multiple chips can be integrated for high performance. CoWoS stands at the forefront of this heterogeneous integration, having been widely adopted in Nvidia’s GPUs and becoming a de facto standard for AI computing. AMD’s embrace of CoWoS, following Nvidia, clearly indicates that major AI chip manufacturers consider this technology essential. This trend presents a significant business opportunity for OSAT providers, with companies like ASE/SPIL, Amkor, and Powertech Technology investing heavily in expanding CoWoS capacity and technical expertise. Morgan Stanley’s forecast emphasizes that CoWoS is not merely a single technology but a new growth driver for the semiconductor industry in the AI era.
Strategic Significance & Outlook
The projected 93% surge in CoWoS demand will further accelerate investment and innovation within the semiconductor industry, particularly in the advanced packaging sector. With Nvidia continuing to drive significant demand and AMD entering the CoWoS market, both technological competition and adoption are expected to intensify. OSAT providers will need to rapidly scale up their CoWoS and related 2.5D/3D packaging capabilities to meet this demand, although HBM supply and equipment availability may remain potential bottlenecks. In the long term, the evolution of CoWoS technology and improvements in its cost efficiency will enable its deployment in a wider array of AI applications, further expanding the AI chip market size. This forecast serves as a critical re-evaluation for investors, researchers, and engineers, underscoring advanced packaging as an extremely strategic domain within the semiconductor ecosystem.
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