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3D Metrology explained: Hybrid bonding defect detection specs
Semiconductor Engineering USA Overview 3D metrology is critically enhancing defect detection in advanced semiconductor packaging, particularly for hybrid bonding, to prevent costly failures. This technology precisely measures fine bump h... -
AMD: Taiwan packaging and substrate capacity for 2027/2028
BigGo Finance Taiwan Overview AMD CEO Lisa Su visited Taiwan to secure advanced process technology, packaging, and substrate capacity for 2027 and 2028, ensuring smooth shipments of next-generation AI server products. While TSMC accelera... -
HBM4: SK hynix and Samsung 16-layer vs NVIDIA 12-layer specs
The Korea Herald South Korea Overview Despite NVIDIA's Vera Rubin AI platform favoring 12-layer HBM4 chips, SK hynix and Samsung Electronics are aggressively pursuing 16-layer HBM4 technology. Samsung leads in hybrid copper bonding for h... -
GlobalFoundries: $2B TSMC CoWoS interposer US production timeline
IDC Nova USA Overview GlobalFoundries and TSMC have signed a 5-year, $2 billion agreement for GlobalFoundries to manufacture silicon interposers for TSMC’s CoWoS advanced packaging ecosystem. This strategic partnership will significantly... -
Ultra C and Ultra ECP: PLP yield and cost efficiency specs
chiplet-marketplace.com Global Overview Ultra C vac-p and Ultra ECP ap-p systems have been developed to overcome critical cleaning and plating challenges in Panel-Level Packaging (PLP). Ultra C vac-p is essential for flux residue removal... -
NVHBM: Micron’s bandwidth and power specs for NVIDIA
The Elec Inc. USA Overview Micron Technology announced its custom HBM product, NVHBM, developed for NVIDIA, will utilize outsourced base dies. NVIDIA states NVHBM integrates a customized physical layer (PHY) to reduce I/O PHY package are... -
Intel EMIB: 2.5D packaging for HBM and logic explained
bestpcbs.com USA Overview Intel's EMIB (Embedded Multi-die Interconnect Bridge) is a 2.5D packaging technology that connects adjacent dies via small silicon bridges embedded within the package substrate, achieving high-bandwidth links. W... -
zHBM: Samsung’s vertical stacking and HBM4 performance specs
MK South Korea Overview Samsung Electronics has doubled HBM4's I/O pin count compared to HBM3E, significantly accelerating data transfer with AI accelerators. The company is developing zHBM, a next-generation vertical stacking technology... -
HBM Packaging: Samsung vs SK Hynix patent competition in 2026
BigGo Finance South Korea Overview Samsung Electronics and SK Hynix have filed competing patents in the U.S. for advanced HBM packaging, aiming to enhance efficiency and reliability. Samsung proposes integrating pre- and post-bonding ins... -
HBM4E: Samsung’s 4nm base die and thermal specs for NVIDIA
East Asia Brief South Korea Overview Samsung Electronics has developed an advanced HBM4E thermal management solution featuring a 4nm logic-based die and hybrid copper bonding (HCB), slashing thermal resistance by over 20% compared to HBM...
