New Technology– category –
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IMAPS Device Packaging Conference 2026 Details 3D/2.5D Packaging Advances: FOPLP, Hybrid Bonding Drive Demand
IMAPS USA Overview Professional Development Courses at IMAPS Device Packaging Conference 2026 provided in-depth insights into current and future 3D/2.5D packaging processes and technologies. Key innovations like Fan-Out Panel Level Packa... -
IDTechEx Analyzes New 2.5D/3D Semiconductor Packaging Trends: Glass Interposers and Hybrid Bonding Drive Evolution
IDTechEx UK Overview IDTechEx's analysis highlights glass interposers and hybrid bonding as critical emerging trends in semiconductor packaging. Glass interposers offer compatibility with panel-level packaging, promising cost-effective, ... -
AI Accelerates Shift to Panel Level Packaging (PLP) and Glass Core Substrates, Positioning Them as Pillars of Next-Gen Packaging
IEEE / Presentation USA Overview Driven by soaring demand from AI, automotive electronics, and consumer devices, advanced packaging is a critical enabler for enhanced performance, higher integration, and miniaturization in semiconductors... -
APC 2026: Advanced Packaging, Interconnects, and Chiplets Propel AI Systems Beyond Traditional Scaling
SEMI Europe Europe Overview The Advanced Packaging Conference (APC) 2026 convened to address the critical role of power delivery and interconnect innovations in driving AI system performance. As traditional device scaling approaches its ... -
ECTC 2026 Highlights Advanced Packaging Future: Glass Substrates and FOPLP at the Core of System Innovation
Advanced Packaging Magazine USA Overview ECTC 2026 emphasized a structural shift in semiconductor innovation, moving beyond transistor scaling to packaging and integration technologies. Noteworthy advancements in heterogeneous integratio... -
TSMC Achieves 98-99% Yield for AI Products on CoWoS 5.5x Process, Targets 14x Reticle Size Expansion by 2029
Wccftech Taiwan Overview TSMC Vice President Ho Chun announced remarkable 98% to 99% yields for multiple AI-related products assembled using the CoWoS 5.5x process. This exceptional achievement highlights TSMC's manufacturing prowess in ... -
TSMC Doubles Advanced Packaging Capacity Over Three Years; Samsung Expands 2nm & Advanced Packaging Collaboration with Broadcom
BigGo Finance Taiwan Overview TSMC revealed it has doubled its advanced packaging capacity annually for the past three years but still lags behind surging AI chip demand, operating 10 dedicated facilities globally. Meanwhile, Samsung Ele... -
Samsung Unveils zHBM, a 3D Logic-Memory Integrated AI Architecture, Alongside HBM4E/HBM5 Roadmap at FMS 2026
Samsung Semiconductor South Korea Overview Samsung presented its vision for next-generation AI infrastructure at FMS 2026, unveiling its HBM roadmap, including HBM4E and HBM5, and a novel 3D memory architecture called zHBM. This zHBM sol... -
JEDEC Relaxes HBM4 Package Height to 775 µm, Enabling 12-Hi/16-Hi Stacks Without Immediate Cu-Cu Hybrid Bonding
Exponential Industry USA Overview JEDEC has relaxed the HBM4 package height specification from 720 µm to 775 µm, allowing for 12-Hi and 16-Hi stack HBM modules without immediate reliance on Cu-Cu hybrid bonding. HBM utilizes 3D stacked D... -
NVIDIA Accelerates Feynman AI Platform; TSMC Ramps SoIC Capacity to 50K Wafers/Month by 2027
Benzinga Taiwan Overview NVIDIA is expediting the roadmap for its next-generation Feynman AI platform, prompting TSMC to significantly boost its advanced packaging capabilities. TSMC is rapidly expanding its SoIC technology production, a...
