1. Why materials decide performance — the length of the ring-down, and losses that add up

Start with an everyday feeling

When you strike a bell, the sound rings for a long time. That “length of the ring-down” corresponds to a qubit's T₁ (its lifetime). Even if the bell itself is good metal, a loose fitting, rust or a dirty surface makes the ring die away quickly. It is not only the metal's quality inside (the bulk) but also the places it touches (surfaces and interfaces) that decide the ring-down.

A qubit is the same. Place and co-workers write that the relaxation times of superconducting qubits (transmons) are orders of magnitude shorter than the limits set by the bulk properties of the constituent materials, and that the cause appears to lie in uncontrolled surfaces, interfaces and contaminants Sourced [Reference 1]. Siddiqi's review likewise says that going from bulk materials to working devices introduces amorphous films and non-equilibrium excitations (electronic and phononic), and that the resulting dissipation and fluctuations limit state-of-the-art qubits and processors [Reference 6].

Think of losses as a sum

The energy a qubit loses is the sum of the losses at many places in the device. Wang and co-workers showed that the relaxation rate of a transmon is roughly proportional to the fraction of electric-field energy stored in the surface dielectric layers (the surface participation), and said that dielectric loss at material interfaces is a main factor limiting T₁ Sourced [Reference 14]. As formulas (our commentary; these are general relations):

• 1/Q = Σ (participation p_i × loss tangent tanδ_i): for each place i, multiply “how much of the electric field reaches it (p)” by “how lossy that material is (tanδ)” and add them up
• T₁ = Q ÷ ω = Q ÷ (2π f): the larger Q is, the longer it lasts. f is the qubit frequency

Let us get a feel for the numbers. Take f = 5 GHz (an assumed example). Q = 10⁶ gives T₁ of about 32 µs, Q = 10⁷ gives about 320 µs, and Q = 2.5 × 10⁷ gives about 0.8 ms Our calculation. One more. Verjauw and co-workers report the loss tangent of niobium pentoxide, Nb₂O₅, which forms on niobium surfaces, as tanδ = 9.9 × 10⁻³ [Reference 12]. Suppose 10⁻⁴ of the electric-field energy sits in this oxide (an assumed value). Then 1/Q = 10⁻⁴ × 9.9 × 10⁻³ = about 10⁻⁶, so Q is about 10⁶, and at 5 GHz T₁ is about 32 µs Our calculation. Even an extremely thin film can cut a qubit's lifetime by nearly a factor of ten if its loss tangent is large.

Where does the loss happen? — a cross-section of the device

A transmon is built by making capacitor electrodes from thin metal films on a substrate, with a small Josephson junction between them. The electric field passes through the substrate and the metal surfaces between the electrodes. Loss can occur anywhere the field passes.

The table is our summary (Our calculation). Numbers match Fig. 3. Each value is as stated in the individual paper; devices, substrates, temperatures and photon numbers differ.

2. Materials and fabrication of superconducting qubits — junctions, oxides, substrates, spread

Superconducting qubits are one of the main approaches in today's quantum computers, and their materials and manufacturing problems are the best studied. Here we look at (1) how the Josephson junction at the heart of the qubit is made, (2) the surface oxide, (3) tantalum, niobium and the substrate, and (4) the spread between junctions, in that order. For how a superconducting qubit works, see our explainer on superconducting qubits. For an overview of the field see the review by Kjaergaard and co-workers [Reference 28], and for a classic review of the materials of superconducting qubits see Oliver and Welander [Reference 8].

2.1 What a Josephson junction is — two superconductors with an extremely thin wall between them

A Josephson junction is a structure with a very thin insulating film sandwiched between two superconductors. Pairs of superconducting electrons (Cooper pairs) pass through this thin wall by “tunnelling.” Kreikebaum and co-workers describe the transmon as “a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator” Sourced [Reference 18]. The aluminium-based junctions used for qubits have three layers: aluminium (Al), its oxide (AlOx), and aluminium again [References 15, 18].

What does “anharmonic” mean? An ordinary oscillator such as a swing (a harmonic oscillator) has energy steps spaced equally. With equal spacing, an operation that lifts 0 to 1 also acts in the same way on 1 to 2, so you cannot pick out just 0 and 1. The junction makes the spacing slightly uneven. As an analogy, it is like adding “bumps” to the rungs of an evenly spaced ladder so that only the 0 and 1 rungs can be told apart (our own analogy for explanation). Hertzberg and co-workers write that transmons are weakly anharmonic, with transition energies that decrease at higher levels [Reference 17].

2.2 How a junction is made — evaporating from an angle to make an overlap

Aluminium-based junctions have long been made by angled (shadow) evaporation. The origin is the method using a resist “bridge” reported by Dolan in 1977 [Reference 24], and bridge-free methods (such as the Manhattan style) are also used [References 18, 25]. The flow is shown in Fig. 4.

What matters to a materials engineer is step 3, the oxidation, and the dimensions. The tunnelling current depends extremely sensitively (exponentially, a general physical fact) on the thickness of the wall, so slight differences in oxidation pressure, time and temperature become differences in the junction resistance (R_n) (our commentary). Kreikebaum and co-workers report that when 64 chips of 1 × 1 cm were made from a 150 mm wafer by simply transplanting a recipe optimised for single devices, the room-temperature tunnelling resistance drifted by ±30% across the wafer; in a systematic study of 38 wafers they optimised uniform ashing, ultrasonically assisted resist development and dynamic oxidation (oxidation with gas flowing continuously) Sourced [Reference 18].

Another trick is removing parasitic junctions. Osman and co-workers state that, for shadow-evaporated aluminium junctions, a “patch” joining the junction electrodes to the surrounding wiring is normally made in a separate lithography step; the patch is needed to remove parasitic junctions, which can be a major source of dielectric loss. They showed a method (PICT junctions) that makes electrodes and patch together with one lithography step and one vacuum cycle, giving devices with mean T₁ above 50 µs (Q > 1.5 × 10⁶) Sourced [Reference 15].

2.3 The biggest cause of loss is the surface oxide

As we saw in Section 1, loss is set by the material where the electric field passes. Among the candidates, the oxide that forms on the metal surface is important. Niobium (Nb) has long been used as a superconducting material, but in recent years it has become clear that its surface oxide, niobium pentoxide Nb₂O₅, is lossy. The countermeasures are summarised in Fig. 5.

• Niobium oxide: Verjauw and co-workers studied niobium resonators whose native oxide had been removed with hydrofluoric acid (HF), varying the time they were exposed to air. With 16 minutes of exposure, loss was an order of magnitude lower, with single-photon internal Q reaching up to 7 × 10⁶. As the oxide grew, loss increased in proportion to the Nb₂O₅ thickness, giving a loss tangent of tanδ = 9.9 × 10⁻³. Nb₂O₅ was the only oxide that grew significantly in the first 200 hours Sourced [Reference 12]
• Where the loss is: Altoé and co-workers selectively modified the interface dielectrics of niobium-on-silicon resonators and showed that most TLS loss comes from the silicon surface oxide, while most non-TLS loss is distributed through the niobium surface oxide. Modifying the interfaces after fabrication cut TLS loss by 85% and non-TLS loss by 72%, giving single-photon Q above 5 million Sourced [Reference 11]
• Capping: Bal and co-workers passivated the niobium surface with another material (a cap) to prevent the niobium oxide forming. T₁ was 2 to 5 times longer than in conventional niobium devices with niobium oxide, and with a tantalum cap the median T₁ exceeded 300 µs, with a maximum of 600 µs. They also state that niobium oxide is lossier than the native oxides of tantalum, aluminium and titanium nitride (TiN) Sourced [Reference 4]
• Comparing materials: Wang and co-workers compared Ta, Nb and Al films with the same design and the same junction process, reporting that Ta was best, followed by Al, then Nb, and inferring that the difference comes from the loss of the oxide at the metal–air interface. Dry etching of Ta gave a best T₁ of 503 µs Sourced [Reference 2]

2.4 Tantalum, niobium and the substrate — putting reported values side by side

Fig. 6 collects recently reported values of T₁. This is not a ranking. The qubit frequency, the design, the measurement method and whether the value is an average or a best value differ from report to report.

Each value is as stated in the abstract of each paper. Because the qubit frequency, number measured and average-versus-best differ, please do not compare them side by side to judge superiority.

2.5 Junction spread — a few nanometres of difference becomes a “frequency collision”

So far we have talked about “the lifetime of one qubit,” but a quantum computer must run many qubits at once. What then becomes a problem is the spread in qubit frequencies.

A qubit's frequency is set almost entirely by the junction resistance R_n. Hertzberg and co-workers showed, on 31 qubits, that the spread of frequencies could be explained almost entirely by the spread of junction resistance, and that f is proportional to roughly R_n to the power −1/2 [Reference 17]. As a formula, δf / f ≈ ½ × δR / R. In the measurements, a frequency spread σ_f of 132.3 MHz (2.3% of the median) corresponded to a junction-resistance spread of 4.6%, exactly twice Sourced [Reference 17]. From Osman and co-workers' 3.7% (across the wafer), the frequency is estimated to vary by about 1.7 to 2.5% [Reference 15].

Why is that a problem? If neighbouring qubits end up at the same frequency, they exchange energy and operation errors increase. It is like two neighbouring piano strings tuned to the same note: when you play one, the other sounds (our own analogy for explanation). Hertzberg and co-workers sorted such “frequency collisions” into seven types; for instance, a collision is when the frequencies of neighbouring qubits coincide to within ±17 MHz (estimated as the region where gate error exceeds about 1%) Sourced [Reference 17].

Let us feel the numbers. The qubits of Hertzberg and co-workers (the two groups after tuning) have median frequencies of about 5.43 GHz and 5.70 GHz. A 1% shift in resistance shifts frequency by about 0.5%, so for a 5.43 GHz qubit that is about 27 MHz Our calculation. This is larger than the ±17 MHz window above. Matching junction resistance to within 1% is a demand that severe.

There are two broad kinds of countermeasure.

• Make the spread small during fabrication: Kreikebaum and co-workers brought the relative standard deviation of critical current for 3,000 junctions to below 3.5% across 49 cm², and to an average of 1.8% (below 1.0% in some places) within a 1 × 1 cm window Sourced [Reference 18]. Osman and co-workers report a mean of 3.7% across the wafer and 2.7% within a chip for more than 3,600 junctions, and estimate that 60 to 70% of the frequency variation comes from fluctuations in junction area and the rest from non-uniformity of the tunnel junction [Reference 15]
• Fix it after fabrication: Hertzberg and co-workers used a laser to heat the junctions and change R_n by calibrated amounts (selective laser annealing). Thirty-one junctions were brought to two target resistances with σ_R = 0.61%, and the frequency spread improved from 132.3 MHz to 14.0 MHz, a 9.5-fold improvement Sourced [Reference 17]. Their statistical calculations also show that without tuning the probability of finding a collision-free layout is almost zero, and that with σ_f = 10 MHz, for a distance-5 lattice, a “heavy-hex” lattice is collision-free with probability about 92% and an ordinary square lattice about 0.8% [Reference 17]. The authors state that these techniques and models are already used in available quantum systems (a company's claim)

2.6 Quasiparticles and radiation — noise that comes from outside the material

In a superconductor the electrons are bound in pairs (Cooper pairs). The electron-like excitations that appear when a pair breaks (quasiparticles) take energy away from the qubit. In theory the number produced by heat should be tiny, but experiments had long shown that the real number is orders of magnitude higher than the theoretical value. Vepäläinen and co-workers presented evidence that one cause is environmental radiation (radioactive decay in surrounding materials, and cosmic rays), and reported that this radiation would limit T₁ of today's type of qubit to the millisecond regime, and that adding shielding reduces radiation and tends to lengthen coherence time Sourced [Reference 19]. The same paper notes that infrared photons were already known to increase quasiparticles.

Worse, many qubits can be broken at once. McEwen and co-workers directly observed high-energy particles hitting a large quantum processor. A particle that strikes ionises the substrate and high-energy phonons spread; they showed that bursts of quasiparticles simultaneously and severely limit the energy coherence of all qubits, causing chip-wide failure Sourced [Reference 20]. Quantum error correction presumes that errors occur “independently and small,” so the authors say that simultaneous errors are especially dangerous.

Countermeasures have also been reported. Cardani and co-workers measured in a lead-shielded cryostat deep underground and reported that the frequency of quasiparticle bursts fell by a factor of 50 and dissipation by up to a factor of 4 Sourced [Reference 21]. This does not mean, however, that “put the quantum computer underground” has been settled as the answer. What can be read from it is that the longer a qubit lives, the less negligible factors from outside the material (radiation, infrared) become (our commentary).

2.7 How a laboratory makes it, and how a foundry makes it

Most of the high T₁ values so far are values for a few devices made by laboratory methods (electron-beam writing, angled evaporation, lift-off). To make hundreds or thousands of qubits at the same quality, the methods of a semiconductor factory (a foundry) are needed.

The imec paper states in its abstract that it presents large-scale wafer-wide statistics for transmons made on a 300 mm CMOS pilot line. The entries under “Strengths” on the laboratory side are this article's commentary.

• imec (academic paper): Van Damme and co-workers reported that transmons made on a 300 mm CMOS pilot line with industrial fabrication methods (optical lithography and RIE only) had relaxation and coherence times exceeding 100 µs. They say performance and yield are in line with laboratory-style methods Sourced [Reference 16]
• Google (academic paper): on a 105-qubit processor the mean T₁ of the qubits is 68 µs and T₂ (CPMG) is 89 µs. The authors attribute this to improved fabrication techniques, participation-ratio engineering and optimisation of circuit parameters Sourced [Reference 22]. The point that the average at this scale is about an order of magnitude shorter than the “laboratory best values” in Fig. 6 is the gap we saw earlier
• IBM (company technical blog): in a blog dated 12 November 2025, IBM announced that its quantum processors (Loon and Nighthawk) and future chips on its roadmap are made at the Albany NanoTech Complex in New York using 300 mm wafer technology. It also says that some wafers are cored down to 200 mm for additional custom steps (a company claim) [Reference 29]. The blog gives no performance values such as T₁. It also says that for quantum, the materials and tools differ from those of ordinary semiconductors

3. Materials of other approaches — silicon, diamond, ions, topological

In approaches other than superconducting ones too, “the quality of the material decides performance.” The review by de Leon and co-workers sums up the materials challenges of five approaches to quantum computing [Reference 7]. To connect with other articles in this series, the table gives only the materials points. For details, see each article.

Each number is as stated in the individual paper. They are not for ranking the approaches.

4. Cryogenic wiring and heat — the budget set by cooling power

The dilution refrigerator that cools qubits to between a few mK and 20 mK (see our explainer on cryogenics and control) has a severe upper limit on how much it can cool. On top of that, the wiring (coaxial cables) that drives the qubits carries heat from room temperature to the cold stages. For a materials engineer this means that the thermal conductivity of materials can directly set how large a quantum computer can be.

4.1 The refrigerator's “budget”

Fig. 10 shows the temperature and cooling power of each stage of the commercial dilution refrigerator (Bluefors XLD400) used in the paper by Krinner and co-workers. The lower the temperature, the cooling power becomes smaller by orders of magnitude. The cooling power of the lowest stage (the mixing chamber, MXC) is 19 µW at 20 mK (when 40 mW of heating is applied to the still) Sourced [Reference 23]. 19 µW is about one fifty-thousandth of 1 W Our calculation.

4.2 Heat from wiring — a simple calculation for a feel of the scale

Krinner and co-workers calculated that running 50 qubits needs 124 RF lines in total (50 drive, 50 flux, 8 output, 8 input, 8 amplifier pump). The heat load on the MXC is about 30% of that stage's cooling power (with passive heat and active heat from signal dissipation roughly equal), the operating temperature is about 14 mK, and if the capacity for coaxial cables could be tripled, 150 qubits could be operated Sourced [Reference 23].

Here is a simple division. Dividing the MXC's 19 µW (at 20 mK) by 124 lines gives about 0.15 µW per line (150 nW). With 1,000 lines it would be about 19 nW per line Our calculation (the cooling power is the value at 20 mK, whereas the paper's design is at 14 mK, and heat is not shared out line by line, so this is a rough calculation to get a feel for orders of magnitude). In other words, as qubits increase, the heat allowed per line shrinks rapidly. Krinner and co-workers also write that for about 1,000 qubits the design must be revisited: making the flux lines superconducting NbTi to remove active heat, tolerating a cold plate at about 200 mK (cooling power of at least 400 µW), and tolerating a base temperature of 30 mK (cooling power about 40 µW) [Reference 23].

• Blocking infrared: infrared radiation creates quasiparticles and shortens T₁. Krinner and co-workers describe the option of installing an infrared filter made of Eccosorb CR-124 absorber just before the attenuator at the MXC (6 dB attenuation at 6 GHz) [Reference 23]. It is an example of an absorbing material protecting a qubit's lifetime
• Supply of helium-3: dilution refrigerators use helium-3. In 2009 Science reported that a helium-3 shortage could freeze low-temperature research (as in the article's title) [Reference 30]. We have not, however, checked the later supply and price (Section 6)

5. What limits performance — sorting out the factors

Here we sort what we have covered by the question “what is limiting performance?” There is no single culprit; the limiting factor changes with the stage a qubit has reached. The positioning below is this article's own summary based on what has been reported.

“Positioning” is this article's summary based on the statements of each paper; it does not mean the authors give the same ordering.

A small calculation: why surface and bulk are both needed

Loss is a sum (1/Q = Σ participation × loss tangent). Crowley and co-workers report that in Ta resonators the surface and bulk TLS contributions are comparable [Reference 13]. Suppose the surface loss (1/Q_surface) and the bulk loss (1/Q_bulk) are exactly equal and there is no other loss. Then 1/Q = 2/Q_surface, so Q = Q_surface / 2. Even if the bulk loss were removed completely, Q would only double. To go further, the surface loss must also come down Our calculation (a simplified model of this article; real devices have other losses too). It points the same way as the conclusion of Crowley and co-workers, that improvements in both surface and bulk are needed.

6. What we could not confirm, and a summary

What we could not confirm

• Latest performance and yield on production lines: we checked the values of imec and Google, but IBM's blog (a company claim) gives no performance values, and we have not exhaustively checked other companies or values from 2026 onward [References 16, 22, 29].
• Examples of introducing new materials such as tantalum into a foundry production line: we could not confirm any.
• The microscopic nature of TLS: Müller and co-workers' review describes it as an unresolved question [Reference 10]. We have not exhaustively checked later progress.
• Reproduction of Bland et al.'s Ta on high-resistivity Si on larger chips or on a production line: not confirmed. What the paper has is a time-averaged Q of 9.7 × 10⁶ across 45 qubits and a statement that it could potentially be made at wafer scale [Reference 3].
• The latest supply and price of helium-3: we have only the title of a 2009 news report [Reference 30] and have not checked the current situation.
• Cooling power of newer dilution refrigerators: only the values for the one model of Krinner et al. [Reference 23].
• Standards specific to the materials and manufacture of qubits: we could not confirm any (Section 7).
• Materials issues of non-solid-state approaches such as photonic and neutral-atom, and research programmes and company efforts in Japan: not covered in this article.

7. How to read evaluations and standards

The performance of materials and manufacturing is measured by the internal Q and loss tangent of resonators, the T₁ and T₂ of qubits, junction spread (σ), yield, and cooling power and heat load. No single number tells you enough. On the standards side, an international standard for the vocabulary of quantum computing has been published, but a dedicated standard for measuring material loss or manufacturing quality could not be confirmed within the scope of our survey.

The table is our summary (Our calculation). Numbers are reference numbers. Numbers, titles and status of standards were checked on the official ISO pages (checked 16 October 2026). Because the text of standards is paid, we limit ourselves to titles and scope.

Cautions in reading (for materials engineers)

• Best values and values that match are different: the T₁ of 1.68 ms is the maximum for one device, and 68 µs is the average of a 105-qubit chip. They differ by more than a factor of ten, which is the core of this article [3, 22]
• T₁ depends on frequency: to compare materials, look at Q or the loss tangent. Values at different frequencies, photon numbers and temperatures cannot be compared as they stand [9]
• A company announcement is a company claim: announcements with no performance values, or introductions of a company's own manufacturing, like IBM's blog, are not treated as fact until they can be checked against primary sources (papers) [29]
• Note what is “not there” in standards: we could not confirm a dedicated standard for measuring material loss or manufacturing quality. Because there is none, the reader has to check each paper's measurement method and reporting format. Semiconductors, cryogenic vessels and superconductivity each fall under separate standards bodies [33]
• Plans and achievements are different: a draft such as IEEE P7130 is Not yet confirmed. IBM's roadmap and future chips on 300 mm are also plans

8. Glossary

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37. IEEE SA "IEEE P7130 Standard for Quantum Technologies Definitions (draft)", IEEE SA (the page could not be accessed this time and its status was not re-checked) — standards.ieee.org/ieee/7130/10680/

10. Claim-to-source audit

Last updated: 16 October 2026. Sources are limited to primary ones (peer-reviewed papers, reviews, arXiv papers, IBM's technical blog (a company claim), and the official pages of ISO and NIST). Values such as T₁ differ in qubit frequency, design and measurement method, and do not indicate superiority. Where a worked example uses an assumed value or assumption, the text says so. We could not confirm, and so do not state, the latest performance on production lines, the introduction of new materials into production, standards specific to the materials and manufacture of qubits, or the latest status of IEEE P7130. All figures are explanatory concept diagrams or drawings of reported values; Figs. 1 and 9 are ImageGen-generated conceptual illustrations.