Google’s Next-Gen TPUs Adopt Intel EMIB Packaging, Achieve Yield Targets in First Mass Production

August 30, 2026

digitimes Taiwan

Overview

Google has successfully implemented Intel’s Embedded Multi-die Interconnect Bridge (EMIB) packaging technology for mass production of its next-generation TPUs, already achieving yield targets. This strategic move, in collaboration with MediaTek, addresses the increasing cost and capacity constraints of TSMC’s CoWoS, diversifying Google’s advanced packaging supply chain. The successful adoption is poised to open significant opportunities for Intel in the high-performance computing market, potentially leading to EMIB’s sustained use in future TPU iterations.

In Depth

Key Findings

Google has successfully adopted Intel’s Embedded Multi-die Interconnect Bridge (EMIB) packaging technology for its next-generation Tensor Processing Units (TPUs) in mass production, already achieving critical yield targets. This adoption stems from EMIB meeting Google’s stringent criteria across technical performance, cost-efficiency, and production capacity, positioning it as a viable alternative to TSMC’s constrained CoWoS technology. This collaboration also sees MediaTek deepening its partnership with Google as an ASIC co-development partner.

Technical / Clinical Details

Intel’s EMIB facilitates high-density interconnections between multiple semiconductor dies within a single package, bypassing the need for a full-size silicon interposer characteristic of TSMC’s CoWoS (Chip-on-Wafer-on-Substrate). By utilizing localized silicon bridges, EMIB simplifies the manufacturing process, which can lead to lower costs and improved yields, especially for integrating AI accelerators and High Bandwidth Memory (HBM). TSMC’s CoWoS has faced structural bottlenecks, including escalating costs, yield risks, and capacity limitations, making EMIB an attractive alternative. The reported achievement of yield targets in Google’s initial EMIB-powered TPUs underscores the maturity and reliability of this advanced packaging solution.

Background & Context

The burgeoning demand for AI and High-Performance Computing (HPC) has exponentially increased the need for advanced semiconductor packaging. While TSMC’s CoWoS has been a dominant solution due to its superior performance, its supply has been severely constrained, unable to fully meet market demand. In this context, major technology companies like Google are actively seeking to diversify their packaging supply chain and mitigate risks. The successful integration of EMIB by Google signifies a significant shift in the advanced packaging landscape. Furthermore, Taiwan’s Powertech Technology (PTI) is also projected to commence mass production of its panel-level packaging (PiFO) by mid-2027, indicating a broader trend of innovation and increasing competition in the advanced packaging sector.

Strategic Significance & Outlook

Google’s embrace of EMIB offers Intel a substantial opportunity to secure more customers in the advanced packaging domain. The strong likelihood of EMIB’s continued use in future TPU generations suggests its potential to emerge as a new industry standard for AI hardware. This development is expected to have a profound impact on the semiconductor industry’s supply chain strategies, reducing reliance on TSMC’s CoWoS and fostering a more diversified and robust packaging ecosystem. Investors and industry observers will be closely monitoring the broader adoption of EMIB and its potential to reshape market dynamics.

Source: https://www.digitimes.com/news/a20260827PD212/google-mediatek-packaging-intel-tpu.html

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