Key Findings
ASE has introduced a 3D System-in-Package (SiP) solution within its PowerSiP™ platform to enable vertically integrated voltage regulator modules (VRMs). By positioning voltage regulation directly beneath the processor, this vertical architecture reduces parasitic routing losses by 50% or more compared to traditional lateral architectures. The solution is available now for use in AI data centers and high-performance computing (HPC) applications.
Technical Details
The PowerSiP™ vertical integration toolbox utilizes several advanced packaging technologies to overcome density and thickness constraints in space-constrained compute trays:
- Double-sided connected capacitors positioned between coreless substrates.
- Solder-free, substrate-less cap array modules with exposed terminals for PCB or embedded substrate solutions.
- High-aspect-ratio 4:1 copper pin integration to lower packaging impedance.
- Single- or double-sided molding for high-density integration of active and passive components.
Background and Context
The shift toward vertical power delivery is driven by the scaling performance of AI processors. Modern high-performance AI SoCs can exceed kilowatt-level power consumption and require peak currents greater than 1,000 amps at sub-volt levels. In traditional lateral architectures, electricity must travel across the PCB, through interconnects and package substrates, leading to significant routing losses. Reducing the physical distance between the VRM and the processor is critical to minimizing these losses.
Significance and Outlook
The expansion of the PowerSiP™ platform provides a flexible toolbox for developing compact, highly integrated VRMs for next-generation GPUs, TPUs, and custom ASICs. As AI infrastructure moves toward more heterogeneous and modular compute architectures, system-level power efficiency becomes a defining challenge. ASE’s approach addresses the stringent space and performance requirements of AI at scale by shortening the high-current transmission path, translating directly into system-level power savings.
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