Semiconductor Back-End– category –
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TSMC CoWoS Capacity Becomes Major AI Chip Growth Bottleneck: Ramping to 120K Wafers/Month by late 2026 Still Falls Short of Demand
backplane Taiwan Overview TSMC's CoWoS packaging capacity is identified as the most critical bottleneck hindering AI chip evolution. While TSMC plans to quadruple its CoWoS production capacity from approximately 35,000 wafers/month in la... -
KLA’s Advanced Packaging Business Soars, Projecting Over $1.3B Revenue in FY2026 Driven by AI Inspection Demand
Bitget USA Overview KLA Corporation, a global leader in semiconductor process control and yield management, is experiencing rapid growth in its advanced packaging business, driven by the increasing complexity of AI chips. Revenue from th... -
ASMPT Establishes Advanced Packaging Technology Advisory Council to Accelerate AI-Era Innovation
ASMPT Singapore Overview ASMPT has established an Advanced Packaging Technology Advisory Council (TAC) to address the growing importance of advanced packaging for next-generation computing and AI components. The TAC will focus on a broad... -
Semiconductor Back-End Weekly Report May 31, 2026
📄 Weekly Report May 31, 2026 (PDF) — Download Weekly Report May 31, 2026 (PDF) — DownloadDownload 🎙 Podcast May 31, 2026 (MP3) — Play & Download Semiconductor_BackEndEnglishPodcast_20260531.mp3Download -
AMD Explores Powertech’s FOPLP for Next-Generation Zen 7 CPUs, Eyeing Packaging Diversification
TechPowerUp USA Overview AMD is reportedly exploring Powertech Technology's Fan-Out Panel-Level Packaging (FOPLP) for its upcoming "Zen 7" CPUs, codenamed "Grimlock." This move signals AMD's strategic intent to build increasingly complex... -
Korea Addresses HBM Test Equipment Bottleneck by Fostering Domestic Suppliers
eferix.substack.com South Korea Overview South Korea has identified the HBM test equipment bottleneck, historically dominated by foreign companies like Advantest and Teradyne, as a national supply chain vulnerability. In response, SK Hyn... -
Huawei’s “Tao Law” Proposes 1.4nm-Equivalent Chip Density via Logic Folding and Ultra-Fine Hybrid Bonding
China as a System China Overview Huawei has introduced the "Tao Law," a novel semiconductor process development aiming for 1.4nm-equivalent chip density within five years through "Logic Folding." This method distributes logic gates acros... -
Heterogeneous Integration Advances with Hybrid Bonding, Tackling Critical Power and Thermal Challenges for AI and 5G/6G
IndexBox Global Overview Heterogeneous integration, particularly vertical chip stacking with fine-pitch interconnects, is crucial for future AI and 5G/6G electronics, dramatically reducing data travel distances and power consumption. Hyb... -
Tokyo Electron and Samsung Boost Capex for Hybrid Bonding Equipment Amid Advanced Packaging Shift
Mordor Intelligence Japan, South Korea Overview Tokyo Electron and Samsung are significantly increasing capital expenditures for hybrid bonding and general bonding equipment, targeting long-term growth in the Through-Silicon Via (TSV) ma... -
NVIDIA CEO Jensen Huang Projects $150 Billion Annual Investment in Taiwan’s AI Supply Chain
BigGo Finance Taiwan Overview NVIDIA CEO Jensen Huang announced that the company's annual procurement and investment in Taiwan's AI supply chain is projected to reach $150 billion in the future, a tenfold increase from $10-$15 billion fo...
