Korea Institute of Industrial Technology Develops Novel Chip Integration Process Achieving 4x Commercial HBM Density

July 12, 2026

EurekAlert! South Korea

Overview

Researchers at the Korea Institute of Industrial Technology (KITECH) have developed an innovative chip integration process that achieves approximately four times the integration density of commercial High-Bandwidth Memory (HBM). This new technology combines simultaneous chip transfer with highly efficient metallic interconnection formation, dramatically increasing the number of chips that can be integrated within a given space. This breakthrough enables significant advancements in AI semiconductor performance and is expected to have broad applications, particularly in chiplet-based heterogeneous integration.

In Depth

Key Findings

A research team at the Korea Institute of Industrial Technology (KITECH) has developed a groundbreaking chip integration process that achieves approximately four times the integration density compared to existing commercial High-Bandwidth Memory (HBM). This innovative technology allows for a dramatic increase in the number of chips integrated within a limited space by combining simultaneous chip transfer with efficient metallic interconnection formation. This breakthrough holds immense potential to significantly enhance the computational power of AI semiconductors and is expected to find broad applications in next-generation packaging technologies such as chiplet-based heterogeneous integration.

Technical / Clinical Details

The novel process developed by KITECH’s research team first involves precisely placing chips onto a carrier wafer, followed by applying a unique technique for forming metallic interconnections. The core of this technology lies in its ability to efficiently transfer multiple chips simultaneously and create high-density, electrically superior metallic connections compared to previous micro-bump bonding methods. While conventional HBM typically stacks 8 to 12 layers of DRAM dies, this new technology enables even greater stacking or the integration of smaller chips. As a result, it achieves an unprecedented integration density, approximately four times that of commercial HBM, within a given footprint. This promises dramatic improvements in memory bandwidth, reduced data transfer latency, and a significant boost in overall system performance for AI accelerators and high-performance processors. The process is also designed with manufacturing yield and scalability in mind, paving the way for future mass production.

Background & Context

The semiconductor industry is grappling with the physical limits of Moore’s Law, making performance enhancement through mere miniaturization increasingly challenging. Consequently, heterogeneous integration, which combines different types of chips, and the integration of smaller functional blocks (chiplets) are becoming mainstream approaches for next-generation semiconductor design. HBM is already a critical factor determining the performance of AI chips, but its integration density and cost have always been challenges. KITECH’s achievement opens new avenues not only for existing high-performance memory like HBM but also for integrating diverse chips such as CPUs, GPUs, and Application-Specific Integrated Circuits (ASICs) at much higher densities. This technology will provide the immense data processing power and memory bandwidth necessary to efficiently handle complex AI workloads, fostering further advancements in AI. South Korea, a global leader in memory semiconductors, views the development of such advanced packaging technologies as crucial for maintaining its competitive edge.

Strategic Significance & Outlook

The ultra-high-density chip integration process developed by KITECH, published in *Results in Engineering*, has the potential to significantly impact the AI semiconductor market. If commercialized, this technology could lead to AI accelerators that are much smaller yet dramatically more powerful. This could not only improve power efficiency in data centers but also accelerate the adoption of AI in a broader range of applications, including edge AI devices and mobile AI applications. Its applicability to chiplet-based heterogeneous integration is expected to play a vital role in optimizing individual chiplet manufacturing processes while achieving the best overall system performance and cost efficiency. Future efforts will focus on addressing challenges for mass production (cost, yield, reliability) through further R&D and collaboration with industry partners. This breakthrough signifies that the semiconductor industry is entering a new phase of ‘semiconductor skyscrapers.’

Source: https://www.eurekalert.org/news-releases/1135221

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