TSMC’s CoWoS Supply to Reach At Least 200K Wafers Monthly by 2027, Accelerating Expansion to Meet Soaring AI Demand

July 19, 2026

DigiTimes Taiwan

Overview

TSMC is accelerating its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity expansion to meet robust AI chip demand, with market indications suggesting monthly output will reach at least 200,000 wafers by 2027. Equipment makers are awaiting TSMC’s final order allocation, and current lead times of 7-9 months suggest continued constraints before new capacity comes fully online. This expansion is critical for alleviating AI accelerator supply bottlenecks.

In Depth

Key Findings

TSMC is rapidly accelerating the expansion of its CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity to meet the explosive demand for AI chips. Market forecasts indicate that TSMC’s monthly CoWoS output is expected to reach at least 200,000 wafers by 2027, marking a crucial step towards alleviating the supply bottleneck for AI accelerators.

Technical and Clinical Details

CoWoS is a 2.5D/3D packaging technology that integrates multiple chiplets (such as GPUs and HBM) onto a silicon interposer, maximizing AI chip performance by achieving high bandwidth and low power consumption. TSMC’s CoWoS capacity has been the biggest bottleneck influencing the product shipments of major AI chip vendors like Nvidia and AMD, making its expansion an urgent priority for the entire industry. Currently, lead times for the specialized semiconductor manufacturing equipment required for CoWoS production are lengthy, ranging from 7 to 9 months, which prolongs the period until new production capacity becomes available. Equipment manufacturers are awaiting final order allocations from TSMC, which is collaborating with OSAT (Outsourced Semiconductor Assembly and Test) partners like Amkor to expand capacity in addition to its in-house efforts.

Background and Industry Context

The increasing complexity of AI models and the explosive growth in data volume demand unprecedented computational power and data processing speeds from AI chips. As the limitations of traditional 2D chip designs become apparent, advanced packaging technologies like CoWoS have become a primary means to achieve performance improvements beyond Moore’s Law. However, CoWoS manufacturing requires sophisticated technology and substantial capital investment, making technical hurdles high and limiting the number of companies capable of supplying it. Leading AI chip companies, particularly Nvidia, are believed to have secured the majority of CoWoS capacity, thereby restricting access for other players. This supply shortage has led to increased costs and delayed market entry for AI chips, impacting the overall growth of the semiconductor industry.

Strategic Significance and Outlook

TSMC’s target of reaching 200,000 CoWoS wafers by 2027 represents a significant milestone towards stabilizing AI chip supply. This will enable major AI chip vendors like Nvidia and AMD to ship more products, further accelerating the adoption and development of AI technology. However, given the long lead times for equipment and the current order situation, CoWoS supply constraints will not be entirely resolved in the short term. TSMC and its OSAT partners must continue to invest in CoWoS technological innovation and capacity expansion to meet the demands of the AI era. The trajectory of CoWoS supply will remain a key determinant of AI industry development in the coming years.

Source: https://www.digitimes.com/news/a20260710PD226/tsmc-cowos-2027-packaging-capacity.html

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