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IBM: Fault-tolerant logic specs for 156-qubit processor

OpenReview (arXiv) Unknown
Overview
IBM researchers have demonstrated error-corrected memory and fault-tolerant logical operations with a median two-qubit gate fidelity of approximately 99.7% on a 156-superconducting-qubit array (ibm_boston). This achievement involved implementing large-scale dynamic compass codes and redesigning measurement schedules to address inherent component performance inhomogeneities in monolithic superconducting devices. This progress signifies a crucial step towards realizing practical fault-tolerant quantum computers.
In Depth

Key Findings

IBM’s research team has successfully demonstrated error-corrected memory and fault-tolerant logical operations on a 156-superconducting-qubit array (ibm_boston), achieving an impressive median two-qubit gate fidelity of approximately 99.7%. This groundbreaking achievement stems from the successful optimization of large-scale dynamic compass codes and redesigned measurement schedules, specifically tailored to counteract performance inhomogeneities inherent in monolithic superconducting devices.

Technical Details

  • Processor Architecture: The study was conducted on a 156-qubit superconducting processor, ibm_boston, which employs a heavy-hexagonal lattice structure. This architecture is designed to enhance connectivity and integration density among qubits.
  • Compass Code Implementation: Large-scale dynamic compass codes were utilized. These are a type of quantum error-correcting code specifically designed to protect quantum information and actively suppress noise encountered by qubits.
  • Fault-Tolerant Logical Operations: Backed by a median two-qubit gate fidelity of 99.7%, fault-tolerant logical operations were demonstrated. This implies that quantum information held in logical qubits can be protected even if individual physical qubits experience errors, a critical capability for practical fault-tolerant quantum computers.
  • Redesigned Measurement Schedules: To overcome the intrinsic performance inhomogeneities in superconducting qubits, the research team innovated by redesigning measurement schedules. This optimization strategy enabled maximized overall device performance and enhanced error correction efficiency.

Background & Context

The practical deployment of quantum computers necessitates not only an increase in qubit count but also effective techniques for correcting qubit errors. Superconducting qubits are a leading candidate due to their scalability, but they face challenges related to performance variability across individual qubits. IBM’s current research directly addresses these intrinsic inhomogeneities, demonstrating a concrete method for achieving error correction and fault tolerance in large-scale systems. This represents a significant step from the NISQ (Noisy Intermediate-Scale Quantum) era towards truly fault-tolerant quantum computers (FTQC).

Strategic Significance & Outlook

This achievement by IBM marks a crucial advancement in the roadmap towards realizing fault-tolerant quantum computers. The demonstration of error-corrected memory and fault-tolerant logical operations at 99.7% fidelity provides a foundational blueprint for constructing larger, more reliable quantum systems. The progression of this technology will accelerate quantum computers’ capability to solve complex problems in diverse fields such as drug discovery, material science, and financial modeling. Furthermore, the optimized measurement scheduling techniques developed can be applied to other quantum hardware platforms, contributing to the overall advancement of quantum error correction technologies.

Source: https://arxiv.org/html/2610.11658v1

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