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Qualcomm and Huawei: Patent Licensing Terms and Logic Folding Specs

BigGo Finance Taiwan
Overview
Qualcomm has denied reports that it is a net payer to Huawei or that their new multi-year patent licensing agreement includes “Logic Folding” chip technology. The agreement covers cross-licensing in 5G, AI, and computing, alongside Qualcomm’s acquisition of certain non-cellular US patents from Huawei. This dispute highlights the technical significance of Huawei’s 3D stacking approach used in the Kirin 9050 Pro.
In Depth

Key Findings

Qualcomm and Huawei entered a multi-year, broad patent licensing agreement on October 5, covering 5G, computing, artificial intelligence, and networking. While Qualcomm is acquiring specific non-cellular US patents from Huawei, the company explicitly refuted claims that it has become a net payer to Huawei. Furthermore, Qualcomm denied that the agreement involves licenses for Huawei’s “Logic Folding” chip technology, contradicting earlier reports from Bloomberg and Shenzhen TV’s “Shenzhen News.”

Technical Details of Logic Folding

Logic Folding is a technology path within Huawei’s “Tau Scaling Law” framework, introduced by He Tingbo at the IEEE ISCAS 2026 conference. The approach aims to circumvent EUV lithography restrictions by compressing signal delay through vertical stacking rather than transistor shrinking. Key technical specifications include:

  • Architecture: Two bonded active dies working as a single unit using copper-to-copper hybrid bonding.
  • Interconnects: A 1.5-micron hybrid bonding pitch with approximately 50 million interconnect points.
  • Performance Gains: Wire length is reduced by 30%, core routing by 20%, and critical paths by up to 70%.
  • Efficiency: At equivalent performance, power consumption is reduced by 66% for the NPU, 58% for the GPU, and 41% for CPU performance cores.

Implementation in Kirin 9050 Pro

The technology is implemented in the Kirin 9050 Pro chip found in the Mate XT 2 tri-fold phone. Die-level teardowns reveal a face-to-face bonded structure where the upper die contains high-density compute units (CPU execution units, GPU, NPU logic), while the lower die houses the L3 cache, 12MiB system cache, PLL, and I/O interfaces (LPDDR, PCIe, USB). The combined die area exceeds 240 square millimeters, with transistor density increasing to 238 MTr/mm² from 155 MTr/mm².

Significance and Outlook

The controversy over the licensing terms underscores the industry’s interest in Huawei’s ability to maintain performance via 3D stacking. While the official agreement remains confidential, the denial of “Logic Folding” licenses suggests that this specific architectural path remains proprietary to Huawei.

Source: https://finance.biggo.com/news/6520ef39-1dd1-400a-ab83-9290855da6ee

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