Key Findings
The joint research team has demonstrated a modular QEC architecture that achieves a reduction in physical qubit overhead of more than 30x relative to standard 2D surface codes. This is accomplished by connecting small, flat 2D Euclidean planar chips—containing approximately 100 qubits—using sparse, static inter-module boundary couplers arranged in a hyperbolic tiling geometry with a genus g ≥ 2.
Technical Details
The architecture partitions the global QEC code into flat modules of either 72 qubits or 116 qubits by fine-graining closed hyperbolic surfaces with Euclidean lattice patches of side-length L. To manage errors, the system utilizes cat-flagged syndrome extraction circuits to measure stabilizers spanning adjacent modules across boundary seams.
Performance was validated through circuit-level simulations using the SI1000 noise model (p = 0.1%), decoded via the AlphaQubit neural network and correlated minimum-weight perfect matching (MWPM). The results showed high tolerance to elevated inter-module seam noise (p_seam = 1%), maintaining low logical error rates even when inter-chip cable error rates were 10x higher than on-chip gate errors.
To enable universal fault-tolerant logic without additional space overhead, the team implemented:
- Fault-tolerant walking circuits that execute logical gates via code automorphisms (global tiling permutations).
- Modular ribbon extractors—closed ancilla loops attached along module boundaries that are approximately 4.5x smaller than the memory itself.
Background & Context
The study, titled “Low-Overhead Quantum Error Correction with Boundary-Connected Planar Modules,” addresses the challenge of implementing Quantum Low-Density Parity-Check (qLDPC) codes. While qLDPC codes offer high encoding rates, they typically require complex long-range wire crossings; this modular hyperbolic approach bypasses that requirement by using a networked chip geometry.
Significance & Outlook
By reducing the qubit overhead by over 30x and demonstrating resilience against high inter-chip noise, this architecture provides a scalable path toward fault-tolerant quantum computing using smaller, manageable hardware modules rather than monolithic, complex chips.
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