Transistor– tag –
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Sub-2nm Nodes Blur Process Boundaries as Chiplet Integration Drives Increased Thermal Density and Structural Stress, Hybrid Bonding Emerges as Key Solution
Semiconductor Engineering USA Overview At sub-2nm process nodes, shrinking transistors and heightened process sensitivities are blurring traditional manufacturing boundaries, leading to increased thermal density and structural stress in ... -
Industrial Leap: High-Yield GFETs on 200mm Wafers Accelerate Graphene’s CMOS Integration
ACS Publications Belgium Overview A research collaboration, notably involving Imec, has optimized the manufacturing and analysis processes for CMOS-compatible graphene field-effect transistors (GFETs) on 200mm wafers, a critical mileston... -
Georgia Tech and Tianjin University Develop World’s First Functional Graphene Semiconductor with 10x Silicon’s Electron Mobility, Compatible with Existing Chip Infrastructure
Iron Circuit (YouTube) USA, China Overview Researchers from Georgia Tech and Tianjin University have developed the world's first functional graphene semiconductor, achieving electron mobility ten times higher than silicon. Published in N... -
Paragraf Launches 12-Channel Graphene FET Platform ‘PMF2002’ and Real-Time Enterprise Reader
All About Circuits UK Overview Paragraf, a graphene electronics manufacturer, has released the 'PMF2002' 12-channel Graphene Field Effect Transistor (GFET) platform and the 'Enterprise Reader' real-time data acquisition system for resear... -
University of Wisconsin-Madison Achieves Silicon-Beating Performance with Carbon Nanotube Transistors, Accelerating Nanoelectronics
Facebook (University of Wisconsin-Madison, Science Advances) USA Overview Researchers at the University of Wisconsin-Madison have successfully developed carbon nanotube (CNT) transistors that outperform state-of-the-art silicon transisto... -
Cerebras Systems Achieves AI Inference Breakthrough with Wafer-Scale Engine 3: Delivering Ultra-Low Latency and High Throughput for Generative AI
Cerebras Systems Press Release USA Overview Cerebras Systems has announced a significant leap in AI inference capabilities with its Wafer-Scale Engine 3 (WSE-3), demonstrating record-breaking low latency and high throughput for large-sca... -
Taiwan’s NYCU and TSMC Achieve 0.42-Nanometer Semiconductor Interface Breakthrough, Revolutionizing Transistor Performance
ScienceDaily Taiwan Overview Researchers from National Yang Ming Chiao Tung University (NYCU), in collaboration with TSMC Corporate Research, have achieved a 0.42-nanometer breakthrough in atomically thin semiconductors by precisely engi... -
DAC 2026 Highlights ‘True Challenges of AI Chip Creation’: Debating Design Complexity and Soaring Costs
EE Times USA Overview At the 2026 Design Automation Conference (DAC), a session on 'The True Challenges of AI Chip Creation' emphasized the extreme complexity and escalating costs of the design and manufacturing processes. AI chips face ... -
Lithography-Free Electrical Contact Method Established for 2D Materials and Van der Waals Heterostructures
MDPI Switzerland Overview This study introduces silver paint micromanipulation (SPMM) as a tabletop, lithography-free electrical contacting method for 2D materials and van der Waals heterostructures. This additive, room-temperature appro... -
IMEC, TSMC, Intel, and Samsung Pursue Atomically-Thin 2D Transistors to Sustain Moore’s Law Beyond Silicon in 2026
Internet Pros USA Overview As silicon transistors approach scaling limits, industry leaders IMEC, TSMC, Intel, and Samsung are shifting to atomically-thin 2D semiconductors for next-generation chips. Materials like molybdenum disulfide (...
