Transistor– tag –
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Breaking the Nanometer Barrier: University of Tokyo Unveils World’s Smallest 1nm Semiconducting Nanotubes
Academic Jobs Japan Overview University of Tokyo researchers, led by Associate Professor Yusuke Nakanishi, have successfully fabricated the world's smallest semiconducting nanotubes, measuring an unprecedented one nanometer in diameter. ... -
Precise Doping Control in Pd-Filled CNT Transistors Halves Contact Resistance and Quadruples On-Current, Accelerating Carbon Electronics
Wiley (Small) International Overview A new study established a controllable doping strategy for single-walled carbon nanotube (SWCNT) transistors by combining palladium (Pd) encapsulation and electron beam irradiation. This innovative ap... -
Applied Materials Unveils New ALD and Selective Etch Systems to Advance 3D Chip Scaling
Stock Titan (Company Press Release) USA Overview Applied Materials announced new deposition (Centris Spectral SiN ALD) and selective etch systems to advance 3D chip scaling. The Centris Spectral SiN ALD system is designed for uniform, lo... -
Samsung Unveils Industry’s Smallest 3D Stacked FET at VLSI Symposium for AI/HPC, Boosting Performance and Power Efficiency
MK South Korea Overview Samsung Electronics presented groundbreaking research on the industry's smallest "3D stacked FET" technology at the 2026 VLSI Symposium, earning the Best Paper award among over 1,000 submissions. This innovative a... -
Monolithic Integration of CNT-Based CFETs with 3D-Stacked Photodiodes Achieved, Realizing Unified Sensing and Computing Systems
ACS Nano USA Overview This research successfully demonstrates the monolithic integration of carbon nanotube (CNT)-based complementary field-effect transistors (CFETs) with 3D-stacked photodiodes. Leveraging CNTs' excellent electrical and... -
IMEC, ASML, TSMC Scale 2D Material Transistors to 300mm Wafers, Achieving 50nm Contact Poly Pitch for Fab Integration
IMEC ベルギー Overview IMEC, in partnership with ASML and TSMC, has unveiled a robust, scalable 300mm integrated process for n-type and p-type field-effect transistors utilizing 2D materials. Presented at the 2026 IEEE/JSAP VLSI Technolo... -
Park Systems Invests in Advanced Nanoscale Metrology Portfolio to Drive Next-Gen 3D Packaging and Logic Research
PR Newswire USA Overview Park Systems, a global leader in AFM and nanoscale metrology, announced a strategic investment in its advanced metrology portfolio for 3D packaging and logic research. This initiative aims to accelerate the evolu... -
Atomic Precision Unleashed: ALD and ALE Drive Next-Gen Semiconductor Miniaturization and Performance
ELE Times India Overview Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) are emerging as critical nanoscale processes essential for advancing next-generation semiconductor device miniaturization and performance. These techno... -
Breaking the Barrier: POSTECH Engineers Drastically Reduce Contact Resistance in Ultra-Thin Te Transistors for Next-Gen Electronics
Mirage News South Korea Overview Researchers at POSTECH have achieved a significant breakthrough in nanotechnology by dramatically lowering the contact resistance in ultra-thin tellurium (Te) transistors. This innovation, published in *A... -
Carbon Nanotubes Emerge as Prime Post-Silicon Candidate, Promising Sub-10nm Performance Gains
Nanotechnology Perceptions Netherlands Overview Carbon Nanotubes (CNTs) are emerging as a leading candidate for post-silicon logic, propelled by three exceptional properties: quasi-ballistic transport with mean free paths over 1µm enabli...
