Key Findings
Alice & Bob has reported experimental results showing macroscopic bit-flip lifetimes that exceed one hour. Specifically, the company measured an average idle bit-flip lifetime of 44 minutes on a single-qubit device. On the 12-qubit Helium 2 processor, multi-qubit runs demonstrated stability exceeding three to four hours.
Technical Details
The hardware utilizes cat qubits, which stabilize quantum information in superpositions of coherent states within superconducting microwave cavities. This approach uses two-photon dissipation to exponentially suppress bit-flip errors, though it results in a linear increase in phase-flip noise.
- Monitoring: In a 61-hour continuous monitoring run on a single-cavity test device (pumped to an average occupation of 11 photons), the team recorded 41 discrete quantum jump events.
- Analysis: Bayesian and autocorrelation analysis confirmed single-exponential, memoryless Poisson statistics consistent with Markovian switching.
- Coherence: To ensure stability did not compromise coherence, researchers tracked state parity decay and performed continuous Bloch-sphere Z rotations, achieving a 94.2% gate fidelity in 26.5 ns.
Background & Context
These results provide empirical backing for the error-model assumptions used in Alice & Bob’s previous compilation of Shor’s algorithm. While an idealized model for factoring RSA-2048 on 22,593 qubits assumed a 100-year bit-flip lifetime, the company’s fault-tolerant model indicates that a physical bit-flip rate of once per hour can be corrected. This is achieved by concatenating cat qubits into an outer distance-3 bit-flip code, which would expand the required processor size to approximately 45,000 qubits.
Significance & Outlook
The demonstration confirms that physical devices can operate within the necessary concatenation threshold during idle periods, addressing a primary bottleneck in bosonic quantum error correction. The next technical milestone is to sustain these lifetimes during two-qubit entangling operations, such as bias-preserving CNOT gates, before active logical error correction can be fully realized.
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