New Technology– category –
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POSTECH Develops Heat-Releasable Medical Patch with Shape-Memory Pyramid Structure, Minimizing Skin Damage for Fragile Skin
CHOSUNBIZ South Korea Overview A research team from Pohang University of Science and Technology (POSTECH), in collaboration with Texas Tech and Northwestern Universities, has developed a medical adhesive patch with adjustable adhesion, s... -
KAIST Develops Glucose-Derived Bio-Hot-Melt Adhesive from E. coli, Outperforming Petroleum Counterparts on Stainless Steel
EurekAlert! Science News South Korea Overview Researchers at KAIST have engineered E. coli to produce novel bio-based hot-melt adhesive polymers (poly(4HB-co-PhLA) and poly(3HB-co-4HB-co-PhLA)) from glucose, presenting a sustainable alte... -
Semiconductor Equipment & Materials Market for HBM, Chiplets, and Low-CTE Materials Forecasted to Outpace Overall Wafer Equipment Growth
Mobility Foresights India Overview A Mobility Foresights report projects that the semiconductor equipment and materials market supporting sub-3nm logic, HBM, and chiplet integration will grow faster than the overall wafer equipment marke... -
Semiconductor Progress Bottleneck Shifts from Circuit Design to New Material Integration and Interfacial Control
Astra Trainer USA Overview Astra Trainer reports that the primary constraint on semiconductor advancement has shifted from circuit design to the integration of novel materials. Device failures often occur at interfaces, not within bulk m... -
Panel Warpage Control Emerges as Key Bottleneck Hindering FOPLP Cost Advantage in Advanced Packaging
EAA Partners - Substack USA Overview Panel warpage control is identified as a critical bottleneck preventing Fan-Out Panel Level Packaging (FOPLP) from realizing its theoretical cost advantages in advanced semiconductor manufacturing. Th... -
Sub-2nm Nodes Blur Process Boundaries as Chiplet Integration Drives Increased Thermal Density and Structural Stress, Hybrid Bonding Emerges as Key Solution
Semiconductor Engineering USA Overview At sub-2nm process nodes, shrinking transistors and heightened process sensitivities are blurring traditional manufacturing boundaries, leading to increased thermal density and structural stress in ... -
Advanced AI Chips Face Intensified Thermal Management Challenges: TSMC Plans 20-Layer HBM Integration in 14x Reticle CoWoS by 2028, Microchannel Cooling Emerges as Key Technology
36Kr China Overview Thermal management has become a critical challenge in advanced-packaged AI chips, particularly due to thermal coupling issues across chiplets in 2.5D, 3D IC, CoWoS, and HBM architectures. TSMC's roadmap for 2028 inclu... -
Advanced Packaging Warpage Mitigation: Research Advances in Incorporating Negative Coefficient of Thermal Expansion Materials into Epoxy Molding Compounds and Underfills
Semiconductor Engineering USA Overview Active research is progressing on utilizing negative coefficient of thermal expansion (CTE) materials in epoxy molding compounds (EMC) and underfills to effectively mitigate warpage in large semicon... -
NIST and UCSD Develop Predictive Modeling for Cure Behavior and Thermal Endurance of Advanced Packaging Epoxy Underfills
Semiconductor Engineering USA Overview Researchers from the National Institute of Standards and Technology (NIST) and the University of California San Diego (UCSD) have published a technical paper detailing a new modeling technique to ac... -
SK Hynix Breakthrough: Mass Reflow Underfill Molding Overcomes HBM Stacking Thermal Challenges, While Micron’s Hybrid Bonding Slashes Power Consumption by 30%
CSIS USA Overview SK Hynix has established a lead in HBM chip stacking by investing heavily in 'Mass Reflow Underfill Molding' (MR-MUF), a novel packaging technique that resolves the thermal and physical constraints of multi-die HBM stac...
