Semiconductor Back-End– category –
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TSMC Unveils SoIC 3D Stacking Roadmap: Achieving 4.5µm Pitch by 2029, Enabling Face-to-Face Chiplet Integration for Fujitsu Monaka CPU
専門メディア Taiwan Overview TSMC has revealed its SoIC (System on Integrated Chips) 3D stacking roadmap, targeting a 4.5-micron pitch by 2029, down from today's 6 microns. This advanced face-to-face (F2F) chiplet stacking technology, pa... -
TSMC Forges Exclusive CoPoS Supply Chain to Secure Next-Gen AI Packaging Dominance
専門メディア Taiwan Overview TSMC is reportedly implementing a highly exclusive supply chain strategy for CoPoS, its next-generation panel-level packaging technology, to solidify its leadership in AI semiconductors. This move, involving ... -
TSMC’s CoWoS Bottleneck Threatens to Delay Google TPU Mass Production to 2027
専門メディア Taiwan Overview Chronic shortages in TSMC's CoWoS advanced packaging capacity are projected to delay mass production of Google's custom AI chips (TPU) until 2027. Despite TSMC's aggressive expansion plans targeting 120,000 w... -
TSMC Accelerates Advanced Packaging Capacity Expansion to Meet Exploding AI Demand
専門メディア Taiwan Overview TSMC is rapidly scaling its advanced CoWoS and SoIC packaging capacity to address the surging demand for AI chips. With 18 new fabs and advanced packaging facilities under construction globally, this expansio...
