Die-to-Die Interconnect– tag –
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IMAPS Device Packaging Conference 2026 PDCs Focus on Advanced Packaging for Chiplets and Heterogeneous Integration, Highlighting Hybrid Bonding
IMAPS USA Overview IMAPS Device Packaging Conference 2026 Professional Development Courses (PDCs) extensively covered "Advanced Packaging for Chiplets and Heterogeneous Integration." The courses defined various 2D to 3.5D IC integrations... -
Fraunhofer IPMS Develops High-Density Chiplet Systems at Wafer Level, Advancing Integration for AI and HPC
Design And Reuse Germany Overview Fraunhofer IPMS has developed high-density chiplet systems at the wafer level, aiming to enhance integration for AI and high-performance computing (HPC) applications. This research contributes to the min... -
Applied Materials Achieves Record $7.91 Billion Revenue in Q2 2026, Advanced Packaging Business to Accelerate Over 50% for AI
MLQ.ai USA Overview Applied Materials reported record revenue of $7.91 billion in Q2 2026, marking a 13% sequential and 11% year-over-year increase, with non-GAAP gross margin reaching 50%, an 80 basis point improvement. The company anti... -
AMD Announces Over $10 Billion Taiwan Ecosystem Investment to Bolster AI Infrastructure and Advanced Packaging Manufacturing
Electronics Engineering Herald - EEHerald USA Overview AMD announced an investment exceeding $10 billion in Taiwan's ecosystem to expand its AI infrastructure and advanced packaging manufacturing capabilities. This significant capital in... -
AMD Commits Over $10 Billion to Taiwan’s AI Ecosystem for Advanced Packaging and EFB Technology Expansion
EE Times Taiwan Overview AMD announced an investment exceeding $10 billion into Taiwan's AI ecosystem, bolstering advanced packaging capabilities and R&D. This initiative specifically targets Elevated Fanout Bridge (EFB) based 2.5D p... -
TSMC Unveils SoIC 3D Stacking Roadmap: Achieving 4.5µm Pitch by 2029, Enabling Face-to-Face Chiplet Integration for Fujitsu Monaka CPU
専門メディア Taiwan Overview TSMC has revealed its SoIC (System on Integrated Chips) 3D stacking roadmap, targeting a 4.5-micron pitch by 2029, down from today's 6 microns. This advanced face-to-face (F2F) chiplet stacking technology, pa...
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