Synopsys A14: TSMC multi-die design and UCIe 64G specs

September 26, 2026September 27, 2026

The Register UK

Overview

Synopsys has expanded its advanced node design collaboration with TSMC, enhancing support for A14 design flows, AI-driven automation, and multi-die systems using CoWoS and Co-packaged optics. Key N2P milestones include PCIe 7.0, HBM4, and UCIe, with additional multi-die power delivery and optical design support. Synopsys demonstrated UCIe-A 32G and 40G silicon integrated with CoWoS-S interposers on N3P test chips, and reported plans for 64G UCIe tape-outs on 2nm and 3nm nodes.

In Depth

Key Findings

Synopsys has expanded its advanced node design collaboration with TSMC, significantly enhancing support for the A14 design flow, AI-driven automation, and comprehensive multi-die systems utilizing CoWoS and Co-packaged optics. Notable milestones for the N2P node include robust support for PCIe 7.0, HBM4, and UCIe. Furthermore, Synopsys has successfully demonstrated UCIe-A 32G and 40G silicon integrated with CoWoS-S interposers on N3P test chips, and has reported plans for 64G UCIe tape-outs on 2nm and 3nm nodes, marking substantial progress towards realizing next-generation chiplet interconnect technology.

Technical Details

A14 Design Flow & AI Automation: The expanded A14 design flow by Synopsys integrates agent AI-driven automation to address the complexities of next-generation semiconductor designs. This is expected to accelerate design cycles and yield optimized results for advanced nodes.
Multi-Die & Optical Design Support: Enhanced design support for multi-die systems using advanced packaging technologies like CoWoS (Chip-on-Wafer-on-Substrate) and Co-packaged optics (CPO) is a key focus. CPO involves integrating optical interconnects directly within the semiconductor package, promising significant improvements in bandwidth and energy efficiency.
UCIe Advancements:
- Key targets for the N2P node include PCIe 7.0, HBM4, and the Universal Chiplet Interconnect Express (UCIe). These are crucial for delivering exponential performance gains in AI/HPC systems.
- Synopsys has successfully demonstrated UCIe-A 32G and 40G silicon integrated with CoWoS-S interposers on N3P test chips. This validates the feasibility and performance of chiplet-to-chiplet communication at high speeds.
- Moreover, the company has reported plans for 64G UCIe tape-outs on 2nm and 3nm nodes. This outlines a clear roadmap towards implementing UCIe at its highest speeds, enabling terabyte-per-second class chiplet-to-chiplet bandwidth for ultra-large multi-die systems.

Background and Context

The semiconductor industry faces the dual challenge of slowing Moore’s Law and escalating performance demands from AI/HPC applications. To address this, the shift from monolithic SoCs to multi-die/chiplet designs is accelerating, underscoring the critical importance of advanced packaging technologies and high-speed interconnects. The collaboration between Synopsys and TSMC is indispensable in driving this industry trend forward.

Strategic Significance and Outlook

The strengthened collaboration between Synopsys and TSMC is poised to accelerate innovation in next-generation AI/HPC chip design. The practical implementation of technologies like UCIe 64G and Co-packaged optics will fundamentally improve data center performance and energy efficiency, enabling further advancements in AI. This partnership is expected to broaden the feasibility of multi-die systems at leading-edge process nodes like 2nm and 3nm, significantly influencing the broader semiconductor industry roadmap.

Source: https://www.inelectronics.co.uk/synopsys-extends-a14-and-multi-die-design-flows/

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