AMD: Taiwan packaging and substrate capacity for 2027/2028

BigGo Finance Taiwan

Overview

AMD CEO Lisa Su visited Taiwan to secure advanced process technology, packaging, and substrate capacity for 2027 and 2028, ensuring smooth shipments of next-generation AI server products. While TSMC accelerates 2nm and CoWoS-L expansion, the actual bottlenecks remain HBM memory supply, bit output degradation, and silicon interposer/packaging test yields. AMD’s MI450 series AI platform, utilizing TSMC’s 2nm and CoWoS, is slated for higher volume shipments in 2027.

In Depth

Key Findings

AMD CEO Lisa Su embarked on a rapid visit to Taiwan to lock in critical production capacity for advanced processes, packaging, and substrates, with a strategic focus on 2027 and 2028. This move aims to ensure the smooth rollout of AMD’s next-generation AI server products, highlighting the immense pressure AI chip demand is placing on the entire semiconductor supply chain.

Technical / Clinical Details

AMD’s MI450 series AI platform leverages TSMC’s cutting-edge 2nm process technology and CoWoS (Chip-on-Wafer-on-Substrate) packaging, which is essential for high-performance AI accelerators. Advanced packaging techniques like CoWoS-L integrate logic dies with multiple HBM (High Bandwidth Memory) stacks on a silicon interposer, achieving extremely high data bandwidth and power efficiency. Although TSMC has announced accelerated expansion of its 2nm and CoWoS-L capacities, the actual supply bottlenecks persist in areas such as HBM memory availability (despite long-term contracts), degraded bit output, and yield challenges in silicon interposers and packaging tests. Securing HBM memory, in particular, directly dictates the final supply volume of AI accelerators.

Background & Context

The explosive growth of AI demand has placed unprecedented strain on the semiconductor industry. Specifically, advanced process nodes, sophisticated packaging, and HBM memory have emerged as the ‘new bottlenecks’ in AI chip manufacturing. Demand for CoWoS packaging from major AI chipmakers like NVIDIA reportedly consumes a significant portion of TSMC’s capacity, with lead times stretching to 52-78 weeks. AMD, striving to expand its market share, faces the urgent challenge of securing production capacity in this highly constrained supply environment. CEO Su’s visit underscores how top-tier AI chip design companies prioritize supply chain stability.

Strategic Significance & Outlook

With AMD planning even higher volume shipments of its MI450 series AI platform in 2027, securing advanced process and packaging capacity is paramount for its growth strategy. If bottlenecks such as HBM memory, interposers, and packaging test yields are not resolved, the overall growth of the AI chip market could be hampered. Close collaboration between AMD and TSMC is key to overcoming these challenges and meeting the demand for next-generation AI infrastructure. Such strategic alliances and investments will continue to be crucial movements toward stabilizing the AI semiconductor supply chain.

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