New Technology– category –
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New Technology
AMD Versal AI Core: Space-grade SoC specs for 15-year missions
AMD Newsroom USA Overview AMD has begun sampling its Versal AI Core XQRVC1902 adaptive SoC in an enhanced space-grade organic lidless package, specifically designed for space missions lasting up to 15 years. This novel package incorporat... -
New Technology
Samsung HBM4: Performance and power efficiency targets for zHBM
MK (Maeil Business Newspaper) South Korea Overview Samsung Electronics is demonstrating strong confidence in supplying higher-specification HBM4 products, anticipating significant price increases next year driven by the rapid performance... -
New Technology
Samsung HBM4E: Thermal management specs for 2026 AI interposers
BigGo Finance South Korea Overview As AI semiconductor interposers are projected to expand by up to 40 times, Samsung Electronics is developing Hybrid Copper Bonding (HCB) and Heat Path Block (HPB) technologies to enhance thermal managem... -
New Technology
Huawei Kirin 9050 Pro: 4.3GHz clock and 2030 timeline
Invest Lingo China Overview Huawei's Kirin 9050 Pro chip shipped utilizing ultra-fine pitch hybrid bonding technology at 1.5 micrometers. This "logic folding technology" directly bonds two chips face-to-face, allowing them to function as... -
New Technology
Rapidus 2nm: AI-driven custom chip manufacturing roadmap
Excite Japan Overview Japan's 2nm short Turnaround Time (TAT) semiconductor manufacturing market is being shaped by Rapidus's unique model. The Rapidus 2nm program integrates advanced Gate-All-Around (GAA) technology, single-wafer proces... -
New Technology
Hybrid Bonding: Imec and EV Group 200nm demo explained
Tara Minunilor Belgium Overview Hybrid bonding, a semiconductor integration technology, directly connects dies or wafers with copper, bypassing traditional solder microbumps. Imec and EV Group demonstrated 200nm copper interconnect pitch... -
New Technology
Synopsys A14: TSMC multi-die design and UCIe 64G specs
The Register UK Overview Synopsys has expanded its advanced node design collaboration with TSMC, enhancing support for A14 design flows, AI-driven automation, and multi-die systems using CoWoS and Co-packaged optics. Key N2P milestones i... -
New Technology
UCIe 3.0 explained: PCIe chiplet integration for AI and HPC
Verification Horizons USA Overview Universal Chiplet Interconnect Express (UCIe) 3.0 is transforming PCIe implementation by providing a standardized interconnect for optimized die-to-die communication in chiplet architectures. This enabl... -
New Technology
TSMC CoWoS: 2028 capacity roadmap and production timeline
SemiWiki USA Overview TSMC plans to double its Chip-on-Wafer-on-Substrate (CoWoS) production capacity to 260,000 300mm wafers per month by 2028, up from 130,000 at the end of 2026. This aggressive expansion addresses the surging demand f... -
New Technology
Samsung Electro-Mechanics and Qualcomm Jointly Develop Organic Bridge for Advanced 2.1D AI Semiconductor Packaging
The Elec South Korea Overview Samsung Electro-Mechanics and Qualcomm have collaborated to develop an 'organic bridge' technology for advanced 2.1D packaging in AI semiconductors. This innovation facilitates high-density, high-bandwidth i...